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MC141543P データシート(PDF) 5 Page - Motorola, Inc |
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MC141543P データシート(HTML) 5 Page - Motorola, Inc |
5 / 14 page MC141543 5 MOTOROLA SYSTEM DESCRIPTION MC141543 is a full–screen memory architecture. Refresh is performed by the built–in circuitry after a screenful of dis- play data has been loaded through the serial bus. Only changes to the display data need to be input afterward. Serial data, which includes screen mapping address, dis- play information, and control messages, are transmitted via one of the two serial buses: M_BUS or SPI (mask option). These two sets of buses are multiplexed onto a single set of wires. Standard parts offer M_BUS transmission. Data is received from the serial port and stored by the memory management circuit. Line data is stored in a row buffer for display and refreshing. During this storing and re- trieving cycle, bus arbitration logic patrols the internal traffic to make sure that no crashes occur between the slower seri- al bus receiver and the fast ‘screen–refresh’ circuitry. After the full–screen display data is received through one of the serial communication interfaces, the link can be terminated if a change of the display is not required. The bottom half of the block diagram contains the hard- ware functions for the entire system. It performs all the AMOSD functions such as programmable vertical length (from 16 lines to 63 lines), display clock generation (which is phase locked to the incoming horizontal sync signal at Pin 5 HFLB), bordering or shadowing, and multiple windowing. COMMUNICATION PROTOCOLS M_BUS Serial Communication This is a two–wire serial communication link that is fully compatible with the IIC bus system. It consists of an SDA bi- directional data line and an SCL clock input line. Data is sent from a transmitter (master) to a receiver (slave) via the SDA line, and is synchronized with a transmitter clock on the SCL line at the receiving end. The maximum data rate is limited to 100 kbps and the default chip address is $7A. Operating Procedure Figure 2 shows the M_BUS transmission format. The mas- ter initiates a transmission routine by generating a start condition followed by a slave address byte. Once the ad- dress is properly identified, the slave will respond with an ac- knowledge signal by pulling the SDA line low during the ninth SCL clock. Each data byte that follows must be eight bits long, plus the acknowledge bit, for a total of nine bits. Ap- propriate row and column address information and display data can be downloaded sequentially in one of the three transmission formats described in the Data Transmission Formats section. In the cases of no acknowlege or comple- tion of data transfer, the master will generate a stop condition to terminate the transmission routine. Note that the OSD_EN bit must be set after all the display information has been sent, in order to activate the AMOSD circuitry of MC141543 so that the received information can be displayed. DATA BYTES ACK STOP CONDITION ACK CHIP ADDRESS SDA SCL START CONDITION 1 9 8 2–7 Figure 2. M_BUS Format DATA TRANSMISSION FORMATS After the proper identification by the receiving device, a data train of arbitrary length is transmitted from the master. There are three transmission formats from (a) to (c) as stated below. The data train in each sequence consists of row ad- dress (R), column address (C), and display information (I), as shown in Figure 3. In format (a), display information data must be preceded with the corresponding row address and column address. This format is particularly suitable for updat- ing small amounts of data between different rows. However, if the current information byte has the same row address as the one before, format (b) is recommended. row addr col addr info Figure 3. Data Packet For a full–screen pattern change that requires a massive information update, or during power–up, most of the row and column addresses of either (a) or (b) formats will be consec- utive. Therefore, a more efficient data transmission format (c) should be applied. This sends the RAM starting row and col- umn addresses once only, and then treats all subsequent data as display information. The row and column addresses will be automatically incremented internally for each display information data from the starting location. The data transmission formats are: (a) R – > C – > I – > R – > C – > I – > . . . . . . . . . (b) R – > C – > I – > C – > I – > C – > I. . . . . . . (c) R – > C – > I – > I – > I – > . . . . . . . . . . . . . To differentiate the row and column addresses when trans- ferring data from master, the MSB (most significant bit) is set, as in Figure 4: ‘1’ to represent row, and ‘0’ for column ad- dress. Furthermore, to distinguish the column address be- tween formats (a), (b), and (c), the sixth bit of the column address is set to ‘1’ which represents format (c), and ‘0’ for format (a) or (b). However, there is some limitation on using mixed formats during a single transmission. It is permissible to change the format from (a) to (b), or from (a) to (c), or from (b) to (a), but not from (c) back to (a) or (b). |
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