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CDCP1803 データシート(PDF) 6 Page - Texas Instruments |
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CDCP1803 データシート(HTML) 6 Page - Texas Instruments |
6 / 19 page CDCP1803 1:3 LVPECL CLOCK BUFFER WITH PROGRAMMABLE DIVIDER SCAS727B − NOVEMBER 2003 − REVISED FEBRUARY 2004 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 LVPECL output driver Y[2:0], Y[2:0] PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fclk Output frequency, see Figure 3 0 800 MHz VOH High-level output voltage Termination with 50 Ω to VDD−2 V VDD−1.18 VDD–0.81 V VOL Low-level output voltage Termination with 50 Ω to VDD−2 V VDD−1.98 VDD–1.55 V VO Output voltage swing between Y and Y, see Figure 3 Termination with 50 Ω to VDD−2 V 500 mV IOZL Output 3-state VDD = 3.6 V, VO = 0 V 5 µA IOZH Output 3-state VDD = 3.6 V, VO = VDD – 0.8 V 10 µA tr/tf Rise and fall time 20% to 80% of VOUTPP, see Figure 7 200 350 ps tskpecl(o) Output skew between any LVPECL output Y[2−0] and Y[2−0] See Note A in Figure 6 15 30 ps tDuty Output duty cycle distortion, see Note 3 Crossing point-to-crossing point distortion −50 50 ps tsk(pp) Part-to-part skew Any Y, See Note B in Figure 6 50 ps CO Output capacitance VO = VDD or GND 1 pF LOAD Expected output load 50 Ω NOTES: 3. For a 800-MHz signal, the 50-ps error would result into a duty cycle distortion of ±4% when driven by an ideal clock input signal. LVPECL input-to-LVPECL output parameter PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tpd(lh) Propagation delay rising edge VOX to VOX 320 600 ps tpd(hl) Propagation delay falling edge VOX to VOX 320 600 ps tsk(p) LVPECL pulse skew VOX to VOX, See Note C in Figure 6 100 ps |
同様の部品番号 - CDCP1803 |
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同様の説明 - CDCP1803 |
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