IRF6617

6

www.irf.com

Fig 17.

Diode Reverse Recovery Test Circuit for N-Channel

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer

P.W.

Period

di/dt

Diode Recovery

dv/dt

Ripple

≤ 5%

Body Diode

Forward Drop

Re-Applied

Voltage

Reverse

Recovery

Current

Body Diode Forward

Current

Driver Gate Drive

Inductor Curent

D =

P.W.

Period

*

+

-

+

+

+

-

-

-

ƒ

„

‚

• Driver same type as D.U.T.

• D.U.T. - Device Under Test

D.U.T



Inductor Current

DirectFET

™ Substrate and PCB Layout, ST Outline

(Small Size Can, T-Designation).

Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.

This includes all recommendations for stencil and substrate designs.

3

4

5

6

7

1

2

1- Drain

2- Drain

3- Source

4- Source

5- Gate

6- Drain

7- Drain