Data Sheet

AD5592R

Rev. C | Page 7 of 42

Parameter

Min

Typ

Max

Test Conditions/Comments

1.1

mA

I/O0 to I/O7 are DACs, internal reference,

gain = 1

1

mA

I/O0 to I/O7 are DACs, external reference,

gain = 1

1.1

mA

I/O0 to I/O7 are DACs and sampled by the

ADC, internal reference, gain = 1

0.78

mA

I/O0 to I/O7 are DACs and sampled by the

ADC, external reference, gain = 1

0.75

mA

I/O0 to I/O7 are ADCs, internal reference,

gain = 1

0.5

mA

I/O0 to I/O7 are ADCs, external reference,

gain = 1

0.45

mA

I/O0 to I/O7 are general-purpose outputs

0.45

mA

I/O0 to I/O7 are general-purpose inputs

1.8

V

AD5592R-1 only

3

µA

AD5592R-1 only

1

All specifications expressed in decibels are referred to full-scale input (FSR) and tested with an input signal at 0.5 dB below full scale, unless otherwise noted.

2

Guaranteed by design and characterization; not production tested.

3

DC specifications tested with the outputs unloaded, unless otherwise noted. Linearity calculated using a code range of 8 to 4095. There is an upper dead band of

4

When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output

devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 33).

TIMING CHARACTERISTICS

Table 3. AD5592R Timing Characteristics

Parameter

Unit

Test Conditions/Comments

33

20

ns min

SCLK cycle time, write operation

50

50

ns min

SCLK cycle time, read operation

16

10

ns min

SCLK high time

16

10

ns min

SCLK low time

15

10

ns min

SYNC falling edge to SCLK falling edge setup time

2

2

µs max

7

7

ns min

Data setup time

5

5

ns min

Data hold time

15

10

ns min

SCLK falling edge to SYNC rising edge

30

30

ns min

Minimum SYNC high time for register write operations

60

60

ns min

Minimum SYNC high time for register read operations

0

0

ns min

SYNC rising edge to next SCLK falling edge

25

25

ns max

SCLK rising edge to SDO valid

250

250

ns min

RESET low pulse width (not shown in Figure 4)

1

When reading an ADC conversion.