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ADRF6820 データシート(PDF) 5 Page - Analog Devices |
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ADRF6820 データシート(HTML) 5 Page - Analog Devices |
5 / 45 page Data Sheet ADRF6820 Rev. C | Page 5 of 45 SYNTHESIZER/PLL SPECIFICATIONS VPOS_5V = 5 V, VPOS_3P3 = 3.3 V, ambient temperature (TA) = 25°C, fREF = 153.6 MHz, fREF power = 4 dBm, fPFD = 38.4 MHz, loop filter bandwidth = 20 kHz, measured at LO output, unless otherwise noted. Table 3. Parameter Test Conditions/Comments Min Typ Max Unit PLL REFERENCE Frequency 12 320 MHz Amplitude 4 14 dBm PLL Step Size1 PFD = 30.72 MHz 468.76 Hz PLL Lock Time2 PFD = 30.72 MHz, charge pump = 500 µA, loop bandwidth = 40 kHz, antibacklash delay = 0.5 ns, charge pump bleed current = 78.125 µA down 5 ms PFD FREQUENCY 24 40 MHz INTERNAL VCO RANGE 2850 5700 MHz REFERENCE SPURS fREF = 153.6 MHz, fPFD = 38.4 MHz, fLO = 1809.6 MHz fPFD/4 <−100 dBc fPFD/2 <−100 dBc fPFD × 1 −90.67 dBc fPFD × 2 −95 dBc fPFD × 3 −97 dBc fPFD × 4 <−100 dBc fPFD × 5 <−100 dBc INTEGRATED PHASE NOISE3 1 kHz to 40 MHz integration bandwidth, PFD = 38.4 MHz, fREF = 153.6 MHz, divide by 4, charge pump = 250 µA, loop bandwidth = 20 kHz, antibacklash delay = 0 ns, charge pump bleed current = 46.8 µA down, LO frequency = 1562.5 MHz 0.6 °rms CLOSED-LOOP PERFORMANCE fLO = 1809.6, fREF = 153.6 MHz, fPFD = 38.4 MHz 20 kHz Loop Filter 10 kHz offset −94.7 dBc/Hz 20 kHz offset −95.8 dBc/Hz 100 kHz offset −113 dBc/Hz 200 kHz offset −122.4 dBc/Hz 600 kHz offset −136.5 dBc/Hz 1 MHz offset −141.5 dBc/Hz 10 MHz offset −153.3 dBc/Hz 40 MHz offset −154.6 dBc/Hz 1 Minimum PLL step size is a function of PFD. Value shown is based on PFD = 30.72 MHz, LO_DIV = 2, and the formula fPFD/65535 × 2/LO_DIV. 2 Lock time is defined as the time it takes from the end of a register write for a change in frequency to the point where the frequency of the output is within 500 Hz of the intended frequency. 3 Measured with a nominal device with normal supply and temperature. |
同様の部品番号 - ADRF6820 |
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同様の説明 - ADRF6820 |
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