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AD7403-8BRIZ データシート(PDF) 6 Page - Analog Devices |
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AD7403-8BRIZ データシート(HTML) 6 Page - Analog Devices |
6 / 25 page Data Sheet AD7403 Rev. B | Page 5 of 24 Parameter Min Typ Max Unit Test Conditions/Comments POWER REQUIREMENTS VDD1 4.5 5.5 V VDD2 3 5.5 V IDD1 30 33.5 mA VDD1 = 5.5 V IDD2 13 16 mA VDD2 = 5.5 V 6.5 8 mA VDD2 = 3.3 V Power Dissipation 237 272 mW VDD1 = VDD2 = 5.5 V 187 211 mW VDD1 = 5.5 V, VDD2 = 3.3 V 1 For fMCLKIN > 16 MHz, mark space ratio is 48/52 to 52/48, VDD1 = 5 V ± 5%. 2 See the Terminology section. 3 Not production tested. Sample tested during initial release to ensure compliance. TIMING SPECIFICATIONS VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, TA = −40°C to +105°C (AD7403-8) or −40°C to +125°C (AD7403), unless otherwise noted. Sample tested during initial release to ensure compliance. It is recommended to read MDAT on the MCLKIN rising edge. Table 3. Parameter Limit at TMIN, TMAX Unit Description Min Typ Max fMCLKIN 5 MHz Master clock input frequency 20 MHz t11 Data access time after MCLKIN rising edge 40 ns VDD2 = 4.5 V to 5.5 V 45 ns VDD2 = 3 V to 3.6 V, AD7403 42 ns VDD2 = 3 V to 3.6 V, AD7403-8 t21 Data hold time after MCLKIN rising edge 12 ns VDD2 = 4.5 V to 5.5 V 17 ns VDD2 = 3 V to 3.6 V t3 Master clock low time 0.45 × tMCLKIN ns fMCLKIN ≤ 16 MHz 0.48 × tMCLKIN ns 16 MHz < fMCLKIN ≤ 20 MHz t4 Master clock high time 0.45 × tMCLKIN ns fMCLKIN ≤ 16 MHz 0.48 × tMCLKIN ns 16 MHz < fMCLKIN ≤ 20 MHz 1 Defined as the time required from an 80% MCLKIN input level to when the output crosses 0.8 V or 2.0 V for VDD2 = 3 V to 3.6 V or when the output crosses 0.8 V or 0.7 × VDD2 for VDD2 = 4.5 V to 5.5 V as outlined in Figure 2. Measured with a ±200 μA load and a 25 pF load capacitance. MCLKIN MDAT 1SEE NOTE 1 OF TABLE 3 FOR FURTHER DETAILS. t4 t1 t2 t3 80% 2.0V OR 0.7 × VDD21 0.8V Figure 2. Data Timing |
同様の部品番号 - AD7403-8BRIZ |
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同様の説明 - AD7403-8BRIZ |
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