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ADXL354CEZ-RL7 データシート(PDF) 10 Page - Analog Devices |
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ADXL354CEZ-RL7 データシート(HTML) 10 Page - Analog Devices |
10 / 42 page ADXL354/ADXL355 Data Sheet Rev. 0 | Page 10 of 42 ADXL355 TOP VIEW (Not to Scale) VSUPPLY X Z Y V1P8ANA VSS V1P8DIG CS/SCL SCLK/VSSIO MOSI/SDA MISO/ASEL 11 10 9 8 1 2 3 4 Figure 6. ADXL355 Pin Configuration Table 8. ADXL355 Pin Function Descriptions Pin No. Mnemonic Description 1 CS/SCL Chip Select for SPI (CS). Serial Communications Clock for I2C (SCL). 2 SCLK/VSSIO Serial Communications Clock for SPI (SCLK). Connect to VSSIO for I2C (VSSIO). 3 MOSI/SDA Master Output, Slave Input for SPI (MOSI). Serial Data for I2C (SDA). 4 MISO/ASEL Master Input, Slave Output for SPI (MISO). Alternate I2C Address Select for I2C (ASEL). 5 VDDIO Digital Interface Supply Voltage. 6 VSSIO Digital Ground. 7 RESERVED Reserved. This pin can be connected to ground or left open. 8 V1P8DIG Digital Supply. This pin requires a decoupling capacitor. If VSUPPLY connects to VSS, supply the voltage to this pin externally. 9 VSS Analog Ground. 10 V1P8ANA Analog Supply. This pin requires a decoupling capacitor. If VSUPPLY connects to VSS, supply the voltage to this pin externally. 11 VSUPPLY Supply Voltage. When VSUPPLY equals 2.25 V to 3.6 V, VSUPPLY enables the internal LDOs to generate V1P8DIG and V1P8ANA. For VSUPPLY = VSS, V1P8DIG and V1P8ANA are externally supplied. 12 INT1 Interrupt Pin 1. 13 INT2 Interrupt Pin 2. 14 DRDY Data Ready Pin. |
同様の部品番号 - ADXL354CEZ-RL7 |
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同様の説明 - ADXL354CEZ-RL7 |
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