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SSD1815 データシート(PDF) 6 Page - List of Unclassifed Manufacturers |
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SSD1815 データシート(HTML) 6 Page - List of Unclassifed Manufacturers |
6 / 35 page SSD1815 6 REV 1.5 03/2000 SOLOMON MSTAT This pin is the static indicator driving output. It is only active in master operation. The frame signal output pin, M, should be used as the back plane signal for the static indicator. The duration of overlapping could be programmable. See Extended Command Table for details. This pin becomes high impedance if the chip is operating in slave mode. M This pin is the frame signal input/output. In master mode, the pin supplies frame signal to slave devices while in slave mode, the pin receives frame signal from the master device. CL This pin is the display clock input/output. In master mode, the pin supplies display clock signal to slave devices while in slave mode, the pin receives display clock signal from the master device. DOF This pin is diaplay blanking control between master and slave devices. In master mode, this pin supplies on/off signal to slave devices. In slave mode, this pin receives on/off signal from the master device. CS1, CS2 These pins are the chip select inputs. The chip is enabled for MCP communication only when both CS1 is pulled low and CS2 is pulled high. RES This pin is reset signal input. Initialization of the chip is started once this pin is pulled low. Minimum pulse width for completing the reset is 1us. D/C This pin is Data/Command control pin. When the pin is pulled high, the data at D7-D0 is treated as display data. When the pin is pulled low, the data at D7-D0 will be tranferred to the command reg- ister. R/W(WR) This pin is microprocessor interface input. When interfacing to an 6800-series microprocessor, this pin will be used as R/W singal input. Read mode will be carried out when this pin is pulled high and write mode when low. When interfacing to an 8080-microprocessor, this pin will be the WR input. Data write operation is initiated when this pin is pulled low when the chip is selected. E(RD) This pin is microprocessor interface input. When interfacing to an 6800-series microprocessor, this pin will be used as the enable sig- nal, E. Read/write operation is initiated when this pin is pulled high when the chip is selected. When interfacing to an 8080-microprocessor, this pin receives the RD signal. Data read operation is initiated when this pin is pulled low when the chip is selected. D7-D0 These pins are the 8-bit bi-directional data bus to be connected to the microprocessor in parallel interface mode. D7 is the MSB while D0 is the LSB. When serial mode is selected, D7 is the serial data input (SDA) and D6 is the serial clock input (SCK). VDD Power supply pin. VSS Ground. VSS1 Reference voltage input for internal DC-DC converter. The volt- age of generated, VEE, equals to the multiple factor times the pro- tential different between this pin, VSS1, and VDD. The multiple factor, 2X, 3X or 4X, is selected by different external capacitor connections. All voltage levels are referenced to VDD. Note: the potential at this input pin must lower than or equal to VSS. VEE This is the most negative voltage supply pin of the chip. It can be supplied externally or generated by the internal DC-DC con- verter. When using internal DC-DC converter as generator, voltage at this pin is for internal reference only. It CANNOT be used for driv- ing external circuitries. C3N, C1P, C1N, C2N and C2P When internal DC-DC voltage converter is used, external capacitor(s) is/are connected between these pins. Different con- nection will result in different DC-DC converter multiple factor, 2X, 3X or 4X. Details please refer to voltage converter section in the block diagram description. VFS This is an input pin to provide an external voltage reference for the internal voltage regulator. The function of this pin is only enabled for the External Input chip models which are required special ordering. For normal chip model, please leave this pin NC. VL2, VL3, VL4 and VL5 (Voltages referenced to VDD) LCD driving voltages. They can be supplied externally or gener- ated by the internal bias divider. They have the following relation- ship: VDD > VL2 > VL3 > VL4 > VL5 > VL6 VL6 This pin is the most negative LCD driving voltage. It can be sup- plied externally or generated by the internal regulator. 1:7 bias 1:9 bias (default) VL2 1/7*VL6 1/9*VL6 VL3 2/7*VL6 2/9*VL6 VL4 5/7*VL6 7/9*VL6 VL5 6/7*VL6 8/9*VL6 PIN DESCRIPTIONS |
同様の部品番号 - SSD1815 |
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同様の説明 - SSD1815 |
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