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LM3475MF データシート(PDF) 10 Page - National Semiconductor (TI) |
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LM3475MF データシート(HTML) 10 Page - National Semiconductor (TI) |
10 / 14 page Design Information (Continued) voltage regulated. The hysteretic control topology is well suited to using ceramic output capacitors. However, ceramic capacitors have a very low ESR, resulting in a 90˚ phase shift of the output voltage ripple. This results in low operating frequency and increased output ripple. To fix this problem a low value resistor could be added in series with the ceramic output capacitor. Although counter intuitive, this combination of a ceramic capacitor and external series resistance provide highly accurate control over the output voltage ripple. An- other method is to add an external ramp at the FB pin as shown in Figure 3. By proper selection of R1 and C2, the FB pin sees faster voltage change than the output ripple can cause. As a result, the switching frequency is higher while the output ripple becomes lower. The switching frequency is approximately: Other types of capacitor, such as Sanyo POSCAP, OS-CON, and Nichicon ’NA’ series are also recommended and may be used without additional series resistance. For all practical purposes, any type of output capacitor may be used with proper circuit verification. Capacitors with high ESL (equivalent series inductance) val- ues should not be used. As shown in Figure 1, the output ripple voltage contains a small step at both the high and low peaks. This step is caused by and is directly proportional to the output capacitor’s ESL. A large ESL, such as in an electrolytic capacitor, can create a step large enough to cause abnormal switching behavior. INPUT CAPACITOR SELECTION A bypass capacitor is required between V IN and ground. It must be placed near the source of the external PFET. The input capacitor prevents large voltage transients at the input and provides the instantaneous current when the PFET turns on. The important parameters for the input capacitor are the voltage rating and the RMS current rating. Follow the manu- facturer’s recommended voltage de-rating. RMS current and power dissipation (PD) can be calculated with the equations below: DIODE SELECTION The catch diode provides the current path to the load during the PFET off time. Therefore, the current rating of the diode must be higher than the average current through the diode, which be calculated as shown: I D_AVE =IOUT x(1−D) The peak voltage across the catch diode is approximately equal to the input voltage. Therefore, the diode’s peak re- verse voltage rating should be greater than 1.3 times the input voltage. A Schottky diode is recommended, since a low forward voltage drop will improve efficiency. For high temperature applications, diode leakage current may become significant and require a higher reverse voltage rating to achieve acceptable performance. P-CHANNEL MOSFET SELECTION The PFET switch should be selected based on the maximum Drain-Source voltage (VDS), Drain current rating (I D), maxi- mum Gate-Source voltage (VGS), on resistance (R DSON), and Gate capacitance. The voltage across the PFET when it is turned off is equal to the sum of the input voltage and the diode forward voltage. The VDS must be selected to provide some margin beyond the sum of the input voltage and Vd. Since the current flowing through the PFET is equal to the current through the inductor, I D must be rated higher than the maximum I PK. During switching, PGATE swings the PFET’s gate from V IN to ground. Therefore, A PFET must be se- lected with a maximum VGS larger than V IN. To insure that the PFET turns on completely and quickly, refer to the PGATE section. 20070120 FIGURE 3. External Ramp www.national.com 10 |
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同様の説明 - LM3475MF |
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