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LMC1992CCN データシート(PDF) 9 Page - National Semiconductor (TI) |
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LMC1992CCN データシート(HTML) 9 Page - National Semiconductor (TI) |
9 / 14 page Applications Information (Continued) TLH10789 – 22 FIGURE 4 The Tone Control Amplifier Increasing the values of C2 and C3 decreases the turnover and inflection frequencies ie the Tone Control Response Curves shown in Typical Performance Curves will shift left when C2 and C3 are increased and shift right when C2 and C3 are decreased With C2 e C3 e 00082 2 dB steps are achieved at 100 Hz and 10 kHz Changing C2 and C3 to 001 mF shifts the 2 dB per step frequency to 72 Hz and 83 kHz If the tone control capacitors’ size is decreased these frequencies will increase With C2 e C3 e 00068 mF the 2 dB steps take place at 130 Hz and 112 kHz FADER FUNCTION The four fader functions are all independently adjustable and therefore no balance control is needed Emulating a balance control is accomplished through software by simul- taneously changing a channel’s front and rear faders by equal amounts To satisfy normal balance requirements the faders have an attenuation range of 40 dB SERIAL COMMUNICATION INTERFACE Figure 5 shows the LMC1992’s timing diagram for its three wire MICROWIRE interface A controller’s data stream can be any length once the correct device address is received by the LMC1992 any number of data bits can be sent the last nine bits occurring before ENABLE goes high are used by the LMC1992 The first two bits in a valid data stream are decoded and used as device address bits The LMC1992 uses a unique address of 10 The LMC1992 will not re- spond to information on the DATA line if any other address is used This allows other MICROWIRE serially programma- ble devices to share the same three-wire communication bus When ENABLE goes high any further serial data is ignored and the contents of the shift register is transferred to the data latches Only when information is received by the data latches do any function or setting changes take place The first three of nine bits select one of the LMC1992s functions The remaining six bits set the select- ed function to the desired value or position A data bit is accepted as valid and clocked into an internal shift register on each rising edge of the signal appearing at the LMC1992s CLOCK input pin Proper data interpretation and operation is ensured when ENABLE makes its falling transition during the time when CLOCK is low Erroneous operation will result if the ENABLE signal makes its falling transition at any other time TLH10789 – 21 Note 1 Negative transition on ENABLE clears previous address Clock must be low during transition Note 2 Additional don’t care states may be inserted here for ease of programming (Optional) Note 3 Positive transition on ENABLE latches in new data if the LMC1992 has been addressed Clock can either be high or low during transition FIGURE 5 Clocking Data into the Standard MICROWIRE Interface (Minimum Number of Bits in Data Stream) 9 |
同様の部品番号 - LMC1992CCN |
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同様の説明 - LMC1992CCN |
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