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TSB43CB43A データシート(PDF) 5 Page - Texas Instruments |
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TSB43CB43A データシート(HTML) 5 Page - Texas Instruments |
5 / 97 page TSB43Cx43A/ TI iceLynx-Micro™ IEEE 1394a-2000 TSB43CA42 Consumer Electronics Solution TEXAS INSTRUMENTS SLLS546F – March 2004 – Revised September 2004 PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TEXAS INSTRUMENTS Copyright 2004, Texas Instruments Incorporated MARCH 12, 2004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 List Of Figures Figure 1. TSB43Cx43 Typical Application .................................................................................................. 10 Figure 2. TSB43Cx43 System Block Diagram ............................................................................................ 11 Figure 3. TSB43CA42 System Block Diagram ........................................................................................... 12 Figure 4. TSB43CA43A Plastic QFP Pin Out ............................................................................................. 13 Figure 5. TSB43CA43A µ*BGA Pin Out .....................................................................................................14 Figure 6. TSB43CA42 Plastic QFP Pin Out................................................................................................ 15 Figure 7. TSB43CA42 µ*BGA Pin Out........................................................................................................16 Figure 8. TSB43Cx43 Memory Map ........................................................................................................... 26 Figure 9. Ex-CPU Access ........................................................................................................................... 30 Figure 10. I/O Type-0 68K + Wait Read ..................................................................................................... 33 Figure 11. I/O Type-0 68K + Wait Write...................................................................................................... 35 Figure 12. I/O Type-1 SH3 Read ................................................................................................................ 37 Figure 13. I/O Type-1 SH3 Write ................................................................................................................ 39 Figure 14. I/O Type-2 M16C SRAM-Like + Wait Read ...............................................................................41 Figure 15. I/O Type-2 M16C SRAM-Like + Wait Write ...............................................................................43 Figure 16. I/O Type-3 MPC850 Read ......................................................................................................... 45 Figure 17. I/O Type-3 MPC850 Write ......................................................................................................... 47 Figure 18. Memory Type ............................................................................................................................. 49 Figure 19. Memory Write............................................................................................................................. 51 Figure 20. Watchdog Timer Waveform ....................................................................................................... 54 Figure 21. Example for Data Pass-Through Function ................................................................................ 57 Figure 22. MPEG2 Serial Burst I/F (TX Mode 1) ........................................................................................ 59 Figure 23. MPEG2 Serial Video Burst I/F With Frame Sync Detect Circuit (TX Mode 2)........................... 60 Figure 24. MPEG2 Serial Video Burst I/F Clock Active Only When Data Is Valid (TX Mode 3)................. 60 Figure 25. MPEG2 Serial Video Burst I/F With Data Valid (TX Mode 4) .................................................... 60 Figure 26. MPEG2 Parallel Burst Video I/F (TX Mode 5) ...........................................................................61 Figure 27. MEPG2 Parallel Video Burst I/F With Frame Sync Detect Circuit (TX Mode 6)........................ 61 Figure 28. MPEG2 Parallel Video Burst I/F With Data Valid (TX Mode 7) ................................................. 61 Figure 29. MPEG2 I/F (TX Mode 8) ............................................................................................................ 62 Figure 30. DV I/F (TX Mode 9).................................................................................................................... 62 Figure 31. MPEG2 Serial Burst Video I/F (RX Mode 1).............................................................................. 63 Figure 32. MPEG2 Parallel Burst Video I/F (RX Mode 2)...........................................................................63 Figure 33. MPEG2 Parallel Burst Video I/F (RX Mode 3)...........................................................................63 Figure 34. DV Parallel Burst Video I/F (RX Mode 4) .................................................................................. 64 Figure 35. Transmit HSDI AC Timing ......................................................................................................... 64 Figure 36. Receive HSDI AC Timing .......................................................................................................... 65 Figure 37. Example 1 Sampling Frequency (fs): 192 kHz, Master Clock Frequency: 256fs ...................... 68 Figure 38. Example 2 Sample Frequency (fs): 48 kHz, Master Clock Frequency: 768fs........................... 68 Figure 39. AC Timing Characteristic on Receiving ..................................................................................... 69 Figure 40. AC Timing Characteristic on Transmitting ................................................................................. 69 Figure 41. TPBP and TPBN Connection..................................................................................................... 77 Figure 42. TPAP, TPAN, and TPBIAS Connection..................................................................................... 78 Figure 43. R0 and R1 Connection .............................................................................................................. 78 Figure 44. FILTER0 and FILTER1 Connection........................................................................................... 78 Figure 45. TPB, TPA, and TPBIAS Connection for Terminated Port (Port is not used)............................. 79 Figure 46. Isochronous FIFOs .................................................................................................................... 84 Figure 47. Asynchronous/ Asynchronous Stream FIFOs ........................................................................... 84 Figure 48. Broadcast Receive FIFO ........................................................................................................... 85 Figure 49. Test Load Diagram .................................................................................................................... 93 |
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同様の説明 - TSB43CB43A |
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