Functional Description

The simplified block diagram below shows the 19-bit data register the 14-bit R Counter and the R15 Latch and the 11-bit

N Counter (intermediate latches are not shown) The data stream is clocked (on the rising edge) into the DATA input MSB first

If the Control Bit (last bit input) is HIGH the DATA is transferred into the R Counter (programmable reference divider) and the

S Latch (power up counter reset) If the Control Bit (LSB) is LOW the DATA is transferred into the N Counter (programmable

divider)

TLW12458 – 1

PROGRAMMABLE REFERENCE DIVIDER (R COUNTER) AND COUNTER RESET (R15 LATCH)

If the Control Bit (last bit shifted into the Data Register) is HIGH data is transferred from the 19-bit shift register into a 14-bit

latch (which sets the 14-bit R Counter) and the 1-bit R15 Latch which can be used to force an immediate load of the R and N

counters during a cold power up condition Serial data format is shown below

TLW12458 – 14

14-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO

(R COUNTER)

Divide

14

R

13

R

12

R

11

R

10

RR

9

R

8

R

7

R

6

R

5

R

4

R

3

R

2

R

1

Ratio

R

3

0

0

0

0

0

000000011

4

0

0

0

0

0

000000100

#

#

#

#

#

#

#

########

16383

1

1

1

1

1

1 1 1 1 1 1 1 1 1

Notes

Divide ratios less than 3 are prohibited

Divide ratio 3 to 16383

R1 to R14 These bits select the divide ratio of the programmable

reference divider

C Control bit (set to HIGH level to load R counter and R15 Latch)

Data is shifted in MSB first

1-BIT COUNTER RESET

(R15 LATCH)

Counter

R

Reset

15

Remove

0

Forced Load

Force

1

Load State

The 1-bit counter reset latch controls

whether the R and N counters are im-

mediately forced to load conditions

N and R latch states are immediately

read into the respective counters

SUGGESTED PROGRAMMING SEQUENCE AFTER COLD POWER-UP

1 Program N counter with desired divide ratio

http

www nationalcom

6