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AD5531BRU データシート(PDF) 4 Page - Analog Devices

部品番号 AD5531BRU
部品情報  Serial Input, Voltage Output 12-/14-Bit DACs
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD5531BRU データシート(HTML) 4 Page - Analog Devices

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REV. 0
–4–
AD5530/AD5531
(VDD = 10.8 V to 16.5 V, VSS = –10.8 V to –16.5 V; GND = 0 V;
RL = 5 k
Ω and CL = 220 pF to GND. All specifications TMIN to TMAX, unless otherwise noted.)
SCLK
SYNC
SDIN
LDAC*
CLR
*
LDAC MAY BE TIED PERMANENTLY LOW IF REQUIRED
t1
DB15
DB14
DB11
DB0
MSB
LSB
t4
t6
t7
t8
t12
t9
t10
t11
t5
t3
t2
Figure 1. Timing Diagram for Standalone Mode
STANDALONE TIMING CHARACTERISTICS1, 2
Parameter
Limit at TMIN, TMAX
Unit
Description
fMAX
7
MHz max
SCLK Frequency
t1
140
ns min
SCLK Cycle Time
t2
60
ns min
SCLK Low Time
t3
60
ns min
SCLK High Time
t4
50
ns min
SYNC to SCLK Falling Edge Setup Time
t5
40
ns min
SCLK Falling Edge to
SYNC Rising Edge
t6
50
ns min
Min
SYNC High Time
t7
40
ns min
Data Setup Time
t8
15
ns min
Data Hold Time
t9
5
ns min
SYNC High to LDAC Low
t10
50
ns min
LDAC Pulsewidth
t11
5
ns min
LDAC High to SYNC Low
t12
50
ns min
CLR Pulsewidth
1Guaranteed by design. Not production tested.
2Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns
(10% to 90% of VDD) and timed from a voltage level of (VIL +VIH)/2.
Specifications subject to change without notice.


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