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AD5451YUJ データシート(PDF) 6 Page - Analog Devices

部品番号 AD5451YUJ
部品情報  8/10/12/14-Bit High Bandwidth Multiplying DACs with Serial Interface
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
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AD5451YUJ データシート(HTML) 6 Page - Analog Devices

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–6–
REV. PrD
AD5450/AD5451/AD5452/AD5453
PRELIMINARY TECHNICAL DATA
TERMINOLOGY
Relative Accuracy
Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after adjusting for zero and full scale and is normally expressed in
LSBs or as a percentage of full scale reading.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adja-
cent codes. A specified differential nonlinearity of -1 LSB max over the operating temperature range ensures monotonic-
ity.
Gain Error
Gain error or full-scale error is a measure of the output error between an ideal DAC and the actual device output. For
these DACs, ideal maximum output is VREF – 1 LSB. Gain error of the DACs is adjustable to zero with external resis-
tance.
Output Leakage Current
Output leakage current is current which flows in the DAC ladder switches when these are turned off. For the
IOUT1 termi-
nal, it can be measured by loading all 0s to the DAC and measuring the IOUT1 current. Minimum current will flow in the
IOUT2 line when the DAC is loaded with all 1s
Output Capacitance
Capacitance from IOUT1 or IOUT2 to AGND.
Output Current Settling Time
This is the amount of time it takes for the output to settle to a specified level for a full scale input change. For these de-
vices, it is specifed with a 100
Ω resistor to ground. The settling time specification includes the digital delay from SYNC
rising edge to the full scale output change.
Digital to Analog Glitch lmpulse
The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-secs or nV-secs depending upon whether the glitch is measured as a current
or voltage signal.
Digital Feedthrough
When the device is not selected, high frequency logic activity on the device digital inputs may be capacitivelly coupled
through the device to show up as noise on the IOUT pins and subsequently into the following circuitry. This noise is digital
feedthrough.
Multiplying Feedthrough Error
This is the error due to capacitive feedthrough from the DAC reference input to the DAC IOUT1 terminal, when all 0s are
loaded to the DAC.
Total Harmonic Distortion (THD)
The DAC is driven by an ac reference. The ratio of the rms sum of the harmonics of the DAC output to the fundamental
value is the THD. Usually only the lower order harmonices are included, such as second to fifth.
THD = 20log
(V
2
2 + V
3
2 + V
4
2 + V
5
2)
V1
Digital Intermodulation Distortion
Second order intermodulation (IMD) measurements are the relative magnitudes of the fa and fb tones generated digitally
by the DAC and the second order products at 2fa-fb and 2fb-fa.
Compliance Voltage Range
The maximum range of (output) terminal voltage for which the device will provide the specified characteristics.
Spurious-Free Dynamic Range(SFDR)
It is the usable dynamic range of a DAC before spurious noise interferes or distorts the fundamental signal. SFDR is the
measure of difference in amplitude between the fundamental and the largest harmonically or nonharmonically related spur
from dc to full Nyquist bandwidth (half the DAC sampling rate or fs/2). Narrow band SFDR is a measure of SFDR over
an arbitrary window size, in this case 50% of hte fundamental. Digital SFDR is a measure of the usable dymanic range of
the DAC when the signal is a digitally generated sine wave.


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同様の説明 - AD5451YUJ

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