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CDCVF25081 データシート(PDF) 1 Page - Texas Instruments |
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CDCVF25081 データシート(HTML) 1 Page - Texas Instruments |
1 / 12 page CDCVF25081 3.3-V PHASED-LOCK LOOP CLOCK DRIVER SCAS671A – OCTOBER 2001 – REVISED FEBRUARY 2003 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Phase-Locked Loop-Based Zero-Delay Buffer D Operating Frequency: 8 MHz to 200 MHz D Low Jitter (Cycle-Cycle): ±100 ps Over the Range 66 MHz to 200 MHz D Distributes One Clock Input to Two Banks of Four Outputs D Auto Frequency Detection to Disable Device (Power Down Mode) D Consumes Less Than 20 µA in Power Down Mode D Operates From Single 3.3-V Supply D Industrial Temperature Range –40°C to 85 °C D 25-Ω On-Chip Series Damping Resistors D No External RC Network Required D Spread Spectrum Clock Compatible (SSC) D Available in 16-Pin TSSOP or 16-Pin SOIC Packages description The CDCVF25081 is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a PLL to precisely align, in both frequency and phase, the output clocks to the input clock signal. The CDCVF25081 operates from a nominal supply voltage of 3.3 V. The device also includes integrated series-damping resistors in the output drivers that make it ideal for driving point-to-point loads. Two banks of four outputs each provide low-skew, low-jitter copies of CLKIN. All outputs operate at the same frequency. Output duty cycles are adjusted to 50%, independent of duty cycle at CLKIN. The device automatically goes into power-down mode when no input signal is applied to CLKIN and the outputs go into a low state. Unlike many products containing PLLs, the CDCVF25081 does not require an external RC network. The loop filter for the PLL is included on-chip, minimizing component count, space, and cost. Because it is based on a PLL circuitry, the CDCVF25081 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization is required following power up and application of a fixed-frequency signal at CLKIN and any following changes to the PLL reference. The CDCVF25081 is characterized for operation from -40 °C to 85°C. FUNCTION TABLE S2 S1 1Y0–1Y3 2Y0–2Y3 OUTPUT SOURCE PLL SHUTDOWN 0 0 Hi-Z Hi-Z N/A. Yes 0 1 Active Hi-Z PLL† No 1 0 Active Active Input clock (PLL bypass) Yes 1 1 Active Active PLL† No † CLK input frequency < 2 MHz switches the outputs to low level Copyright 2001 – 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 CLKIN 1Y0 1Y1 VDD GND 2Y0 2Y1 S2 FBIN 1Y3 1Y2 VDD GND 2Y3 2Y2 S1 D PACKAGE (SOIC) PW PACKAGE (TSSOP) (TOP VIEW) |
同様の部品番号 - CDCVF25081 |
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同様の説明 - CDCVF25081 |
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