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LMK61A2-100M00SIAT データシート(PDF) 7 Page - Texas Instruments |
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LMK61A2-100M00SIAT データシート(HTML) 7 Page - Texas Instruments |
7 / 22 page 7 LMK61E0-050M, LMK61E2-100M, LMK61E2-125M, LMK61E2-156M, LMK61E2-312M LMK61A2-100M, LMK61A2-125M, LMK61A2-156M, LMK61A2-312M, LMK61I2-100M www.ti.com SNAS676B – OCTOBER 2015 – REVISED MARCH 2017 Product Folder Links: LMK61E0-050M LMK61E2-100M LMK61E2-125M LMK61E2-156M LMK61E2-312M LMK61A2- 100M LMK61A2-125M LMK61A2-156M LMK61A2-312M LMK61I2-100M Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated (1) Refer to Parameter Measurement Information for relevant test conditions. (2) Measured max spur level with 50 mVpp sinusoidal signal between 50 kHz and 1 MHz applied on VDD pin (3) DJSPUR (ps, pk-pk) = [2*10(SPUR/20) / (π*fOUT)]*1e6, where PSRR or SPUR in dBc and fOUT in MHz. 6.12 PSRR Characteristics (1) VDD = 3.3 V, TA = 25°C, FS[1:0] = NC, NC PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PSRR Spurs induced by 50-mV power supply ripple(2)(3) at 156.25-MHz output, all output types Sine wave at 50 kHz –70 dBc Sine wave at 100 kHz –70 Sine wave at 500 kHz –70 Sine wave at 1 MHz –70 (1) Refer to Parameter Measurement Information for relevant test conditions. (2) Phase jitter measured with Agilent E5052 signal source analyzer using a differential-to-single ended converter (balun or buffer). (3) Ensured by characterization. 6.13 PLL Clock Output Jitter Characteristics (1) (2) VDD = 3.3 V ± 5%, TA = –40°C to 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RJ RMS phase jitter(3) (12 kHz – 20 MHz) (1 kHz – 5 MHz) fOUT < 100 MHz, integer-N PLL, all output types 200 300 fs RMS RJ RMS phase jitter(3) (12 kHz – 20 MHz) (1 kHz – 5 MHz) fOUT ≥ 100 MHz, integer-N PLL, all output types 100 200 fs RMS (1) Refer to Parameter Measurement Information for relevant test conditions. (2) Phase jitter measured with Agilent E5052 signal source analyzer using a differential-to-single ended converter (balun or buffer). 6.14 Typical 156.25-MHz Output Phase Noise Characteristics (1) (2) VDD = 3.3 V, TA = 25°C, Output Type = LVPECL/LVDS/HCSL PARAMETER OUTPUT TYPE UNITS LVPECL LVDS HCSL phn10k Phase noise at 10-kHz offset –143 –143 –143 dBc/Hz Phn20k Phase noise at 20-kHz offset –143 –143 –143 dBc/Hz phn100k Phase noise at 100-kHz offset –144 –144 –144 dBc/Hz Phn200k Phase noise at 200-kHz offset –145 –145 –145 dBc/Hz phn1M Phase noise at 1-MHz offset –150 –150 –150 dBc/Hz phn2M Phase noise at 2-MHz offset –154 –154 –154 dBc/Hz phn10M Phase noise at 10-MHz offset –165 –162 –164 dBc/Hz phn20M Phase noise at 20-MHz offset –165 –162 –164 dBc/Hz 6.15 Additional Reliability and Qualification PARAMETER CONDITION / TEST METHOD Mechanical Shock MIL-STD-202, Method 213 Mechanical Vibration MIL-STD-202, Method 204 Moisture Sensitivity Level J-STD-020, MSL3 |
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