SDA9220-5 datasheet(11/42 Pages) SIEMENS

部品番号	SDA9220-5

部品情報	Memory Sync Controller III

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メーカー	SIEMENS [Siemens Semiconductor Group]

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SDA 9220-5

Semiconductor Group

127

FRM Delay (subaddress 05)

CFH Control (subaddress 06)

FRM Disable

Control Bit FRDIS (D7)

Frame display signal FRM enable

0

Frame display signal FRM disable (FRM = L)

1

Delay for Frame

Display Signal

Control Bit

FRD 6

(D6)

FRD 5

(D5)

FRD 4

(D4)

FRD 3

(D3)

FRD 2

(D2)

FRD 1

(D1)

FRD 0

(D0)

0 LL1.5 cycles

to

127 LL1.5 cycles

0

1

0

1

0

1

0

1

0

1

0

1

0

1

CFH Width (H level)

Control Bit

CFHW3

(D7)

CFHW2

(D6)

CFHW1

(D5)

CFHW0

(D4)

0 halfline

to

15 halflines

0

1

0

1

0

1

0

1

CFH Position Before VS

Control Bit

CFHP3

(D3)

CFHP2

(D2)

CFHP1

(D1)

CFHP0

(D0)

3 halflines

to

18 halflines

0

1

0

1

0

1

0

1

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