Si4730/31/34/35-D60

Rev. 1.2

7

Figure 1. Reset Timing Parameters for Busmode Select

Table 3. Reset Timing Characteristics1,2,3

Parameter

Symbol

Min

Typ

Max

Unit

RST Pulse Width and GPO1, GPO2/INT Setup to RST



100

—

—

µs

GPO1, GPO2/INT Hold from RST



30

—

—

ns

RST Pulse Release time before VDD/VIO turn off

30

—

—

ns

Important Notes:

1.

When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is

high) does not occur within 300 ns before the rising edge of RST.

2.

When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until

after the first start condition.

3.

When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the

rising edge of RST.

4.

GPO2 low.

5.

RST must be held low for at least 100 µs after all voltage supplies have been ramped up.

6.

RST needs to be asserted (pulled low) prior to any supply voltage being ramped down.