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74LVTH18514DGGRG4 データシート(PDF) 2 Page - Texas Instruments |
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74LVTH18514DGGRG4 データシート(HTML) 2 Page - Texas Instruments |
2 / 38 page SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS670C – AUGUST 1996 – REVISED MARCH 1998 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description (continued) In the normal mode, these devices are 20-bit universal bus transceivers that combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self-test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE universal bus transceivers. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), clock-enable (CLKENAB and CLKENBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched while CLKENAB is high and/or CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low and CLKENAB is low, A data is stored on a low-to-high transition of CLKAB. When OEAB is low, the B outputs are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow, but uses the OEBA, LEBA, CLKENBA, and CLKBA inputs. In the test mode, the normal operation of the SCOPE universal bus transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Std 1149.1-1990. Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions, such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The B-port outputs of ’LVTH182514, which are designed to source or sink up to 12 mA, include equivalent 25- Ω series resistors to reduce overshoot and undershoot. The SN54LVTH18514 and SN54LVTH182514 are characterized for operation over the full military temperature range of –55 °C to 125°C. The SN74LVTH18514 and SN74LVTH182514 are characterized for operation from –40 °C to 85°C. FUNCTION TABLE† (normal mode, each register) INPUTS OUTPUT OEAB LEAB CLKENAB CLKAB A B L L L L X B0‡ L LL ↑ LL L LL ↑ HH L LH X X B0‡ L HX X L L L HX X H H H X X X X Z † A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, LEBA, CLKENBA, and CLKBA. ‡ Output level before the indicated steady-state input conditions were established |
同様の部品番号 - 74LVTH18514DGGRG4 |
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同様の説明 - 74LVTH18514DGGRG4 |
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