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TMP102AIDRLT データシート(PDF) 10 Page - Texas Instruments |
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TMP102AIDRLT データシート(HTML) 10 Page - Texas Instruments |
10 / 30 page TMP102 SBOS397F – AUGUST 2007 – REVISED DECEMBER 2015 www.ti.com Table 4. Address Pin and Slave Addresses DEVICE TWO-WIRE ADDRESS A0 PIN CONNECTION 1001000 Ground 1001001 V+ 1001010 SDA 1001011 SCL 7.3.5 Writing and Reading Operation Accessing a particular register on the TMP102 device is accomplished by writing the appropriate value to the pointer register. The value for the pointer register is the first byte transferred after the slave address byte with the R/W bit low. Every write operation to the TMP102 device requires a value for the pointer register (see Figure 8). When reading from the TMP102 device, the last value stored in the pointer register by a write operation determines which register is read by a read operation. To change the register pointer for a read operation, a new value must be written to the pointer register. This action is accomplished by issuing a slave address byte with the R/W bit low, followed by the pointer register byte. No additional data are required. The master then generates a START condition and sends the slave address byte with the R/W bit high to initiate the read command. See Figure 7 for details of this sequence. If repeated reads from the same register are desired, continually sending the Pointer Register bytes is not necessary because the TMP102 remembers the Pointer Register value until it is changed by the next write operation. Register bytes are sent with the most significant byte first, followed by the least significant byte. 7.3.6 Slave Mode Operations The TMP102 can operate as a slave receiver or slave transmitter. As a slave device, the TMP102 never drives the SCL line. 7.3.6.1 Slave Receiver Mode The first byte transmitted by the master is the slave address, with the R/W bit low. The TMP102 then acknowledges reception of a valid address. The next byte transmitted by the master is the pointer register. The TMP102 then acknowledges reception of the pointer register byte. The next byte or bytes are written to the register addressed by the pointer register. The TMP102 acknowledges reception of each data byte. The master can terminate data transfer by generating a START or STOP condition.. 7.3.6.2 Slave Transmitter Mode The first byte transmitted by the master is the slave address, with the R/W bit high. The slave acknowledges reception of a valid slave address. The next byte is transmitted by the slave and is the most significant byte of the register indicated by the pointer register. The master acknowledges reception of the data byte. The next byte transmitted by the slave is the least significant byte. The master acknowledges reception of the data byte. The master terminates data transfer by generating a Not-Acknowledge on reception of any data byte, or generating a START or STOP condition. 7.3.7 SMBus Alert Function The TMP102 device supports the SMBus alert function. When the TMP102 device operates in Interrupt Mode (TM = 1), the ALERT pin can be connected as an SMBus alert signal. When a master senses that an ALERT condition is present on the ALERT line, the master sends an SMBus alert command (0001 1001) to the bus. If the ALERT pin is active, the device acknowledges the SMBus alert command and responds by returning the slave address on the SDA line. The eighth bit (LSB) of the slave address byte indicates if the ALERT condition was caused by the temperature exceeding THIGH or falling below TLOW. For POL = 0, the LSB is low if the temperature is greater than or equal to THIGH; this bit is high if the temperature is less than TLOW. The polarity of this bit is inverted if POL = 1. See Figure 10 for details of this sequence. If multiple devices on the bus respond to the SMBus alert command, arbitration during the slave address portion of the SMBus alert command determines which device clears the ALERT status. The device with the lowest two- wire address wins the arbitration. If the TMP102 device wins the arbitration, its ALERT pin inactivates at the completion of the SMBus alert command. If the TMP102 device loses the arbitration, its ALERT pin remains active. 10 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TMP102 |
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