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STP16DPP05MTR データシート(PDF) 11 Page - STMicroelectronics |
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STP16DPP05MTR データシート(HTML) 11 Page - STMicroelectronics |
11 / 34 page STP16DPP05 Timing diagrams DocID16518 Rev 4 11/34 5 Timing diagrams Table 9: Truth table CLOCK LE/DM1 OE/DM2 SERIAL-IN OUT0 ............. OUT7 ................ OUT15 SDO _|¯ H L Dn Dn ..... Dn - 7 ..... Dn -15 Dn - 15 _|¯ L L Dn + 1 No change Dn - 14 _|¯ H L Dn + 2 Dn + 2 ..... Dn - 5 ..... Dn -13 Dn - 13 ¯|_ X L Dn + 3 Dn + 2 ..... Dn - 5 ..... Dn -13 Dn - 13 ¯|_ X H Dn + 3 OFF Dn - 13 OUTn = ON when Dn = H OUTn = OFF when Dn = L. Figure 7: Timing diagram 1 Latch and output enable terminals are level-sensitive and are not synchronized with rising or falling edge of CLK signal. 2 When LE/DM1 terminal is low level, the latch circuit holds previous set of data. 3 When LE/DM1 terminal is high level, the latch circuit refreshes new set of data from SDI chain. 4 When OE/DM2 terminal is at low level, the output terminals Out 0 to Out 15 respond to data in the latch circuits, either ‘1’ for ON or ‘0’ for OFF. 5 When OE/DM2 terminal is at high level, all output terminals are switched OFF. |
同様の部品番号 - STP16DPP05MTR |
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同様の説明 - STP16DPP05MTR |
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