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DM8147SCIS0 データシート(PDF) 1 Page - Texas Instruments |
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DM8147SCIS0 データシート(HTML) 1 Page - Texas Instruments |
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1 / 377 page  TMS320DM8148, TMS320DM8147 www.ti.com SPRS647E – MARCH 2011 – REVISED DECEMBER 2013 TMS320DM814x DaVinci™ Video Processors Check for Samples: TMS320DM8148, TMS320DM8147 1 High-Performance System-on-Chip (SoC) 1.1 Features 12 – 32KB of L1D RAM/Cache • High-Performance DaVinci Video Processors – 256KB of L2 Unified Mapped RAM/Caches – Up to 1-GHz ARM® Cortex®-A8 RISC Core With ECC – Up to 750-MHz C674x™ VLIW DSP • System Memory Management Unit (MMU) – Up to 6000 MIPS and 4500 MFLOPS – Maps C674x DSP and EDMA TC Memory – Fully Software-Compatible with C67x+™, Accesses to System Addresses C64x+™ • 128KB of On-Chip Memory Controller (OCMC) • ARM Cortex-A8 Core RAM – ARMv7 Architecture • Imaging Subsystem (ISS) • In-Order, Dual-Issue, Superscalar – Camera Sensor Connection Processor Core • Parallel Connection for Raw (up to 16-Bit) • Neon™ Multimedia Architecture and BT.656 or BT.1120 (8- and 16-Bit) • Supports Integer and Floating Point – Image Sensor Interface (ISIF) for Handling • Jazelle® RCT Execution Environment Image and Video Data From the Camera • ARM Cortex-A8 Memory Architecture Sensor – 32KB of Instruction and Data Caches – Resizer – 512KB of L2 Cache • Resizing Image and Video From 1/16x to – 64KB of RAM, 48KB of Boot ROM 8x • TMS320C674x Floating-Point VLIW DSP • Generating Two Different Resizing – 64 General-Purpose Registers (32-Bit) Outputs Concurrently – Six ALU (32-/40-Bit) Functional Units • Programmable High-Definition Video Image Coprocessing (HDVICP v2) Engine • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double – Encode, Decode, Transcode Operations Precision/64-Bit) Floating Point – H.264, MPEG-2, VC-1, MPEG-4, SP/ASP, • Supports up to Four SP Adds Per Clock JPEG/MJPEG and Four DP Adds Every Two Clocks • Media Controller • Supports up to Two Floating-Point (SP or – Controls the HDVPSS, HDVICP2, and ISS DP) Approximate Reciprocal or Square • SGX530 3D Graphics Engine Root Operations Per Cycle – Delivers up to 25 MPoly/sec – Two Multiply Functional Units – Universal Scalable Shader Engine • Mixed-Precision IEEE Floating-Point – Direct3D Mobile, OpenGLES 1.1 and 2.0, Multiply Supported up to: OpenVG 1.0, OpenMax API Support – 2 SP x SP → SP Per Clock – Advanced Geometry DMA Driven Operation – 2 SP x SP → DP Every Two Clocks – Programmable HQ Image Anti-Aliasing – 2 SP x DP → DP Every Three Clocks • Endianness – 2 DP x DP → DP Every Four Clocks – ARM and DSP Instructions/Data – Little • Fixed-Point Multiply Supports Two 32 x Endian 32 Multiplies, Four 16 x 16-Bit Multiplies • HD Video Processing Subsystem (HDVPSS) Including Complex Multiplies, or Eight 8 x – Two 165-MHz, 2-channel HD Video Capture 8-Bit Multiplies per Clock Cycle Modules • C674x Two-Level Memory Architecture • One 16-/24-Bit Input or Dual 8-Bit SD – 32KB of L1P RAM/Cache With EDC Input Channels 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to Copyright © 2011–2013, Texas Instruments Incorporated specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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