TS68EN360MR33L datasheet(8/82 Pages) ATMEL

部品番号	TS68EN360MR33L

部品情報	32-bitQuad Integrated Communication Controller

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メーカー	ATMEL [ATMEL Corporation]

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8

TS68EN360

2113A–HIREL–03/02

Note:

1. I denotes input, O denotes output and I/O is input/output.

Clock and Test

(Cont’d)

Three-State

TRIS

Used to three-state all pins if QUICC is configured as a

master. Always Sampled except during system reset. (I)

Test Clock

TCK

Provides a clock for Scan test logic. (I)

Test Mode Select

TMS

Controls test mode operations. (I)

Test Data In

TDI

Serial test instructions and test data signal. (I)

Test Data Out

TDO

Serial test instructions and test data signal. (O)

Test Reset

TRST

Provides an asynchronous reset to the test controller. (I)

Power

Clock Synthesizer Power

VCCSYN

Power supply to the PLL of the clock synthesizer.

Clock Synthesizer Ground

GNDSYN

Ground supply to the PLL of the clock synthesizer.

Clock Out Power

VCCCLK

Power supply to clock out pins.

Clock Out Ground

GNDCLK

Ground supply to clock out pins.

Special Ground 1

GNDS1

Special ground for fast AC timing on certain system bus

signals.

Special Ground 2

GNDS2

Special ground for fast AC timing on certain system bus

signals.

System Power Supply and

Return

VCC, GND

Power supply and return to the QUICC.

--

No Connect

NC4-NC1

Four no-connect pins.

Table 1. System Bus Signal Index (Normal Operation) (Continued)

Group

Signal Name

Mnemonic

Function

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