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AD9886 データシート(PDF) 7 Page - Analog Devices |
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AD9886 データシート(HTML) 7 Page - Analog Devices |
7 / 32 page REV. 0 AD9886 –7– PIN FUNCTION DETAIL Inputs RAIN Analog Input for RED Channel GAIN Analog Input for GREEN Channel BAIN Analog Input for BLUE Channel High-impedance inputs that accept the RED, GREEN, and BLUE channel graphics signals, respectively. (The three channels are identi- cal and can be used for any colors, but colors are assigned for convenient reference.) They accommodate input signals ranging from 0.5 V to 1.0 V full scale. Signals should be ac-coupled to these pins to support clamp operation. HSYNC Horizontal Sync Input This input receives a logic signal that estab- lishes the horizontal timing reference and provides the frequency reference for pixel clock generation. The logic sense of this pin is controlled by serial register 0Fh Bit 7 (HSYNC Polarity). Only the leading edge of HSYNC is active, the trailing edge is ignored. When HSYNC Polarity = 0, the falling edge of HSYNC is used. When HSYNC Polarity = 1, the rising edge is active. The input includes a Schmitt trigger for noise immunity, with a nominal input threshold of 1.5 V. Electrostatic Discharge (ESD) protection diodes will conduct heavily if this pin is driven more than 0.5 V above the maximum toler- ance voltage (3.3 V), or more than 0.5 V below ground. VSYNC Vertical Sync Input This is the input for vertical sync. SOGIN Sync-on-Green Input This input is provided to assist with processing signals with embedded sync, typically on the GREEN channel. The pin is connected to a high-speed comparator with an internally gen- erated threshold, which is set to 0.15 V above the negative peak of the input signal. When connected to an ac-coupled graphics signal with embedded sync, it will produce a noninverting digital output on SOGOUT. (This is usually a composite sync signal, containing both vertical and horizontal sync information that must be separated before passing the horizontal sync signal to HSYNC). When not used, this input should be left unconnected. For more details on this func- tion and how it should be configured, refer to the Sync on Green section. CLAMP External Clamp Input This logic input may be used to define the time during which the input signal is clamped to the reference dc level (ground for RGB or midscale for YUV). It should be exercised when the reference dc level is known to be present on the analog input channels, typi- cally during the back porch of the graphics signal. The CLAMP pin is enabled by setting control bit EXTCLMP to 1 (the default power-up is 0). When disabled, this pin is ignored and the clamp timing is determined internally by counting a delay and duration from the trailing edge of the HSYNC input. The logic sense of this pin is controlled by CLAMPOL. When not used, this pin must be grounded and EXTCLMP programmed to 0. COAST Clock Generator Coast Input (Optional) This input may be used to cause the pixel clock generator to stop synchronizing with HSYNC and continue producing a clock at its current frequency and phase. This is useful when processing signals from sources that fail to produce horizontal sync pulses when in the vertical interval. The COAST signal is gener- ally not required for PC-generated signals. The logic sense of this pin is controlled by COAST Polarity. When not used, this pin may be grounded and COAST Polarity programmed to 1, or tied HIGH (to VD through a 10 k Ω resistor) and COAST Polarity programmed to 0. COAST Polarity defaults to 1 at power-up. CKEXT External Clock Input (Optional) This pin may be used to provide an external clock to the AD9886, in place of the clock internally generated from HSYNC. It is enabled by programming EXTCLK to 1. When an external clock is used, all other inter- nal functions operate normally. When unused, this pin should be tied through a 10 k Ω resistor to GROUND, and EXTCLK programmed to 0. The clock phase adjustment still operates when an external clock source is used. CKINV Sampling Clock Inversion (Optional) This pin may be used to invert the pixel sampling clock, which has the effect of shifting the sampling phase 180 °. This is in support of Alternate Pixel Sampling mode, wherein higher-frequency input signals (up to 280 Mpps) may be captured by first sam- pling the odd pixels, then capturing the even pixels on the subsequent frame. This pin should be exercised only during blanking intervals (typically vertical blanking) as it may produce several samples of corrupted data during the phase shift. CKINV should be grounded when not used. |
同様の部品番号 - AD9886 |
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同様の説明 - AD9886 |
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