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データシートサーチシステム |
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TP3410J データシート(PDF) 7 Page - National Semiconductor (TI) |
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TP3410J データシート(HTML) 7 Page - National Semiconductor (TI) |
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7 / 32 page  Functional Description (Continued) 22 Line Transmit Section Data to be transmitted to the line consists of the customer’s 2BaD channel data and the data from the maintenance processor plus other ‘‘spare’’ bits in the overhead chan- nels This data is multiplexed and scrambled prior to addi- tion of the syncword A pulse waveform synthesizer then drives the transmit filter which in turn passes the line signal to the line driver The differential line-driver outputs Loa and Lob are designed to drive a transformer through an external termination circuit A 115 transformer designed as shown in the Applications section results in a signal am- plitude of nominally 25V pk on the line for single quats of the outer (g3) levels Note however that because of the RDS accumulation of the 2B1Q line code continuous ran- dom data will produce signal swings considerably greater than this on the line Short-circuit protection is included in the output stage overvoltage protection must be provided externally 23 Line Receive Section The receive input signal should be derived from the trans- former by means of a coupling circuit as shown in the Appli- cations section At the front-end of the receive section is a continuous filter followed by a switched-capacitor low-pass filter which limits the noise bandwidth A Hybrid Balance Filter provides a degree of analog echo-cancellation in or- der to limit the dynamic range of the composite signal An AD converter then samples the composite received signal prior to the cancellation of the ‘‘echo’’ from the local trans- mitter by means of an adaptive digital transversal filter (ie the ‘‘echo-canceller’’) Following this the attenuation and distortion (inter-symbol interference) of the received signal from the far-end caused by the transmission line are equal- ized by a second adaptive digital filter configured as a Deci- sion Feedback Equalizer (DFE) thereby restoring a ‘‘flat’’ channel response with maximum received eye opening over a wide spread of cable attenuation characteristics From the received line signal a Timing Recovery circuit based on a DPLL (Digital Phase-Locked Loop) recovers a low-jitter clock for optimum sampling of the received sym- bols The MCLK input provides the reference clock for the DPLL at 1536 MHz Received data is then detected with automatic correction for line signal polarity if necessary and a flywheel synchronization circuit searches for and locks onto the frame and superframe syncwords Frame lock will be maintained until errored sync words are detected for 480 ms If a loss-of-sync condition persists for 480 ms the device will cease transmitting and go into a RESET state While the receiver is synchronized data is descrambled us- ing the specified polynomial and the individual channels de- multiplexed and passed to their respective processing cir- cuits Whenever the loop is deactivated either powered up or powered down a Line Signal Detect circuit is enabled to detect the presence of an incoming 10 kHz wake-up tone if the far-end starts to activate the loop The LSD circuit gen- erates an interrupt and if the device is powered down pulls the LSD pin low either of these indicators may be used to alert an external controller which must respond with the appropriate commands to initiate the activation sequence (see the Activation section) 30 ACTIVATION CONTROL OVERVIEW The TP3410 contains an automatic sequencer for the com- plete control of the start-up activation sequence specified in the ANSI standard Both the ‘‘cold-start’’ and the fast ‘‘warm-start’’ are supported Interaction with an external controller requires only Activate Request and Deactivate Request commands with the option of inserting breakpoints in the sequence for additional external control if desired Automatic control of the ‘‘act’’ and ‘‘dea’’ bits in the M4 bit positions is provided along with the specified 40 ms and 480 ms timers used during deactivation A 15 second de- fault timer is also included to prevent system lock-up in the event of a failed activation attempt Section 11 gives an overview of the activation handshake between the TP3410 and the controller See TP3410 User’s Manual AN-913 for additional information 40 MAINTENANCE FUNCTIONS OVERVIEW 41 M Channel Processing In each frame of the superframe there are 6 ‘‘Overhead’’ bits assigned to various control and maintenance functions of the DSL Some processing of these bits may be pro- grammed via the Command Registers while interaction with an external controller provides the flexibility to take full ad- vantage of the maintenance channels New data written to any of the overhead bit Transmit Registers is resynchroniz- ed internally to the next available complete superframe or half-superframe as appropriate In addition the SFS pin may be used to indicate the start of each superframe in 1 direction see Figure 2 and Register CR2 TLH9151 – 26 FIGURE 2 Superframe Sync Pin Timing 7 |
同様の部品番号 - TP3410J |
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同様の説明 - TP3410J |
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