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932SQL456AGILF データシート(PDF) 9 Page - Integrated Device Technology

部品番号 932SQL456AGILF
部品情報  Low-Power CK420BQ Derivative for PCIe Separate Clock Architectures
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メーカー  IDT [Integrated Device Technology]
ホームページ  http://www.idt.com
Logo IDT - Integrated Device Technology

932SQL456AGILF データシート(HTML) 9 Page - Integrated Device Technology

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REVISION B 09/29/15
9
LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES
932SQL456 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 932SQL456. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
Electrical Characteristics–Current Consumption
AC Electrical Characteristics–CPU, SRC, NS_SAS, NS_SRC, DOT96 LP-HCSL
Outputs
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
3.3V Core Supply Voltage
VDDA
4.6
V
1,2
3.3V Logic Supply Voltage
VDD
4.6
V
1,2
Input Low Voltage
VIL
GND-0.5
V
1
Input High Voltage
VIH
Except for SMBus interface
VDD+0.5V
V
1
Input High Voltage
VIHSMB
SMBus clock and data pins
5.5V
V
1
Storage Temperature
Ts
-65
150
°C
1
Junction Temperature
Tj
125
°C
1
Case Temperature
Tc
110
°C
1
Input ESD protection
ESD prot
Human Body Model
2000
V
1
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
TA = TAMB; Supply Voltage VDDx = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
Operating Supply Current
IDD3.3OP
All outputs active @100MHz,
CL = Full load;
217
250
mA
1
Powerdown Current
IDD3.3PDZ
4.3
8
mA
1
1Guaranteed by design and characterization, not 100% tested in production.
TA = TAMB; Supply Voltage VDDx = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
Duty Cycle
tDC
Measured differentially, PLL
Mode
45
49.6%
55
%
Skew, Output to Output
tsk3SRC
Across all SRC outputs,
VT = 50%
23
50
ps
1
Skew, Output to Output
tsk3CPU
Across all CPU outputs,
VT = 50%
24
50
ps
1
CPU, SRC, NS_SAS outputs
6
50
ps
1,3
DOT96 output
5
50
ps
1,3
1Guaranteed by design and characterization, not 100% tested in production.
2 Zo=85Ω (differential impedance).
3 Measured from differential waveform
Jitter, Cycle to cycle
tjcyc-cyc


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