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TS3A225E データシート(PDF) 9 Page - Texas Instruments |
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TS3A225E データシート(HTML) 9 Page - Texas Instruments |
9 / 37 page TS3A225E www.ti.com SCDS329A – AUGUST 2012 – REVISED MAY 2013 I2C INTERFACE TIMING REQUIREMENTS Unless otherwise noted the specification applies over the VDD range and operating junction temp –40°C ≤ TJ ≤ 70°C. STANDARD MODE FAST MODE I2C BUS I2C BUS PARAMETER UNIT MIN MAX MIN MAX fscl I2C clock frequency 0 100 0 400 kHz tsch I2C clock high time 4 0.6 µs tscl I2C clock low time 4.7 1.3 µs tsp I2C spike time 50 50 ns tsds I2C serial-data setup time 250 100 ns tsdh I2C serial-data hold time 0 0 ns ticr I2C input rise time 1000 21 300 ns ticf I2C input fall time 300 21 300 ns tocf I2C output fall time (CL = 10 pF to 400 pF) 300 20+0.1Cb (1) 300 ns tbus I2C bus free time between Start and Stop conditions 4.7 1.3 µs tsts I2C Start or repeat Start condition setup 4.7 0.6 µs tsth I2C Start or repeat Start condition hold 4 0.6 µs tsps I2C Stop condition setup 4 0.6 µs tvd(data) SCL low to SDA output valid 1 1 µs tvd(ack) Valid-data time, ACK from SCL low to SDA low 1 1 µs cb I2C bus load 0 400 0 400 pF (1) Cb = total capacitance of one bus line in pF. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: TS3A225E |
同様の部品番号 - TS3A225E |
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同様の説明 - TS3A225E |
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