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CDCVF2505 データシート(PDF) 3 Page - Texas Instruments

部品番号 CDCVF2505
部品情報  3.3-V Clock Phase-Lock Loop Clock Driver
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
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CDCVF2505 データシート(HTML) 3 Page - Texas Instruments

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1
CLKIN
8
CLKOUT
2
1Y1
7
1Y3
3
1Y0
6
VDD3.3V
4
GND
5
1Y2
Not to scale
3
CDCVF2505
www.ti.com
SCAS640G – JULY 2000 – REVISED AUGUST 2016
Product Folder Links: CDCVF2505
Submit Documentation Feedback
Copyright © 2000–2016, Texas Instruments Incorporated
5 Description (continued)
Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock of
the feedback signal to the reference signal. This stabilization is required following power up and application of a
fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference.
6 Pin Configuration and Functions
D or PW Package
8-Pin SOIC or TSSOP
Top View
(1)
I = Input, O = Output, and P = Power
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
1Y[0–3]
2, 3, 5, 7
O
Clock outputs. These outputs are low-skew copies of CLKIN. Each output has an integrated
25-Ω series damping resistor.
CLKIN
1
I
Clock input. CLKIN provides the clock signal to be distributed by the CDCVF2505 clock
driver. CLKIN is used to provide the reference signal to the integrated PLL that generates the
clock output signals. CLKIN must have a fixed frequency and fixed phase for the PLL to
obtain phase lock. Once the circuit is powered up and a valid signal is applied, a stabilization
time (100 µs) is required for the PLL to phase lock the feedback signal to CLKIN.
CLKOUT
8
O
Feedback output. CLKOUT completes the internal feedback loop of the PLL. This connection
is made inside the chip and an external feedback loop should NOT be connected. CLKOUT
can be loaded with a capacitor to achieve zero delay between CLKIN and the Y outputs.
GND
4
P
Ground
VDD3.3V
6
P
3.3-V supply


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