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AM5718AABCXEQ1 データシート(PDF) 4 Page - Texas Instruments

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部品番号 AM5718AABCXEQ1
部品情報  Sitara Processors Silicon Revision 2.0
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
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AM5718AABCXEQ1 データシート(HTML) 4 Page - Texas Instruments

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AM5718, AM5716
SPRS957D – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
Submit Documentation Feedback
Table of Contents
Copyright © 2016–2017, Texas Instruments Incorporated
Table of Contents
1
Device Overview
......................................... 1
1.1
Features
.............................................. 1
1.2
Applications
........................................... 2
1.3
Description
............................................ 2
1.4
Functional Block Diagram
........................... 3
2
Revision History
......................................... 5
3
Device Comparison
..................................... 6
3.1
Device Comparison Table
............................ 6
4
Terminal Configuration and Functions
.............. 9
4.1
Terminal Assignment
................................. 9
4.2
Ball Characteristics
.................................. 10
4.3
Multiplexing Characteristics
......................... 81
4.4
Signal Descriptions
.................................. 98
5
Specifications
......................................... 140
5.1
Absolute Maximum Ratings
........................ 140
5.2
ESD Ratings
....................................... 141
5.3
Power on Hours (POH) Limits
..................... 141
5.4
Recommended Operating Conditions
............. 142
5.5
Operating Performance Points
..................... 146
5.6
Power Consumption Summary
.................... 164
5.7
Electrical Characteristics
........................... 164
5.8
Thermal Characteristics
............................ 174
5.9
Power Supply Sequences
......................... 175
6
Clock Specifications
................................. 180
6.1
Input Clock Specifications
......................... 181
6.2
DPLLs, DLLs Specifications
....................... 190
7
Timing Requirements and Switching
Characteristics
........................................ 194
7.1
Timing Test Conditions
............................ 194
7.2
Interface Clock Specifications
..................... 194
7.3
Timing Parameters and Information
............... 194
7.4
Recommended Clock and Control Signal Transition
Behavior
............................................ 196
7.5
Virtual and Manual I/O Timing Modes
............. 196
7.6
Video Input Ports (VIP)
............................ 198
7.7
Display Subsystem - Video Output Ports
.......... 217
7.8
Display Subsystem - High-Definition Multimedia
Interface (HDMI)
................................... 227
7.9
Camera Serial Interface 2 CAL bridge (CSI2)
..... 228
7.10
External Memory Interface (EMIF)
................. 228
7.11
General-Purpose Memory Controller (GPMC)
..... 228
7.12
Timers
.............................................. 252
7.13
Inter-Integrated Circuit Interface (I2C)
............. 252
7.14
HDQ / 1-Wire Interface (HDQ1W)
................. 255
7.15
Universal Asynchronous Receiver Transmitter
(UART)
............................................. 257
7.16
Multichannel Serial Peripheral Interface (McSPI)
. 259
7.17
Quad Serial Peripheral Interface (QSPI)
.......... 265
7.18
Multichannel Audio Serial Port (McASP)
.......... 269
7.19
Universal Serial Bus (USB)
........................ 289
7.20
Serial Advanced Technology Attachment (SATA)
. 289
7.21
Peripheral Component Interconnect Express
(PCIe)
.............................................. 289
7.22
Controller Area Network Interface (DCAN)
........ 290
7.23
Ethernet Interface (GMAC_SW)
................... 291
7.24
eMMC/SD/SDIO
................................... 304
7.25
General-Purpose Interface (GPIO)
................ 327
7.26
PRU-ICSS Interfaces
.............................. 328
7.27
System and Miscellaneous interfaces
............. 355
7.28
Test Interfaces
..................................... 355
8
Applications, Implementation, and Layout
...... 359
8.1
Power Supply Mapping
............................ 359
8.2
DDR3 Board Design and Layout Guidelines
....... 360
8.3
High Speed Differential Signal Routing Guidance
. 383
8.4
Power Distribution Network Implementation
Guidance
........................................... 383
8.5
Single-Ended Interfaces
........................... 383
8.6
Clock Routing Guidelines
.......................... 385
9
Device and Documentation Support
.............. 387
9.1
Device Nomenclature
.............................. 387
9.2
Tools and Software
................................ 389
9.3
Documentation Support
............................ 389
9.4
Receiving Notification of Documentation Updates
. 390
9.5
Related Links
...................................... 390
9.6
Community Resources
............................. 390
9.7
Trademarks
........................................ 390
9.8
Electrostatic Discharge Caution
................... 390
9.9
Glossary
............................................ 391
10
Mechanical Packaging and Orderable
Information
............................................. 392
10.1
Mechanical Data
................................... 392


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