CDCVF2505PWR datasheet(5/23 Pages) TI1

部品番号	CDCVF2505PWR

部品情報	3.3-V Clock Phase-Lock Loop Clock Driver

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5

CDCVF2505

www.ti.com

SCAS640G – JULY 2000 – REVISED AUGUST 2016

Product Folder Links: CDCVF2505

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(1)

All typical values are at respective nominal VDD and 25°C

7.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX

UNIT

VIK

Input voltage

II = –18 mA, VDD = 3 V

–1.2

V

VOH

High-level output voltage

IOH = –100 µA, VDD = MIN to MAX

VDD – 0.2

V

IOH = –12 mA, VDD = 3 V

2.1

IOH = –6 mA, VDD = 3 V

2.4

VOL

Low-level output voltage

IOH = 100 µA, VDD = MIN to MAX

0.2

V

IOH = 12 mA, VDD = 3 V

0.8

IOH = 6 mA, VDD = 3 V

0.55

IOH

High-level output current

VO = 1 V, VDD = 3 V

–27

mA

VO = 1.65 V, VDD = 3.3 V

–36

IOL

Low-level output current

VO = 2 V, VDD = 3 V

27

mA

VO = 1.65 V, VDD = 3.3 V

40

II

Input current

VI = 0 V or VDD

±5

µA

CI

Input capacitance

VI = 0 V or VDD, VDD = 3.3 V

4.2

pF

Co

Output capacitance

VI = 0 V or VDD, VDD = 3.3 V

Yn

2.8

pF

CLKOUT

5.2

(1)

Assured by design but not 100% production tested

(2)

Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be

obtained, a fixed-frequency, fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications for

propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not

apply for input modulation under SSC application.

7.6 Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted)

MIN

TYP

MAX

UNIT

SUPPLY VOLTAGE, VDD = 3.3 V ±0.3 V

fclk

Clock frequency

24

200

MHz

Input clock duty cycle

24 MHz to 85 MHz(1)

30%

85%

86 MHz to 200 MHz

40%

50%

60%

Stabilization time(2)

100

µs

SUPPLY VOLTAGE, VDD = 2.7 V

fclk

Clock frequency

42

166

MHz

Input clock duty cycle

42 MHz to 85 MHz(1)

30%

70%

86 MHz to 166 MHz

40%

50%

60%

Stabilization time(2)

100

µs

同様の部品番号 - CDCVF2505PWR

メーカー	部品番号	データシート	部品情報
Texas Instruments	CDCVF2505PWR	369Kb / 14P	[Old version datasheet] 3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER
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	CDCVF2505PWRG4	549Kb / 14P	[Old version datasheet] 3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER

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同様の説明 - CDCVF2505PWR

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