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TSE2004GB2C0NCG データシート(PDF) 6 Page - Integrated Device Technology

部品番号 TSE2004GB2C0NCG
部品情報  DDR4 Temperature Sensor with Integrated 4Kbit EEPROM for Memory Module
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メーカー  IDT [Integrated Device Technology]
ホームページ  http://www.idt.com
Logo IDT - Integrated Device Technology

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©2017 Integrated Device Technology, Inc.
May 15, 2017
TSE2004GB2C0 Datasheet
Serial Communications
The TSE2004GB2C0 includes a 4 kilobit serial EEPROM organized as two pages of 256 bytes each, or 512 bytes of total memory. Each
page is comprised of two 128 byte blocks. The device is able to selectively lock the data in any or all of the four 128-byte blocks.
Designed specifically for use in DRAM DIMMs (Dual Inline Memory Modules) with Serial Presence Detect, all the information concerning
the DRAM module configuration (such as its access speed, its size, its organization) can be kept write protected in one or more of the
blocks of memory.
The TSE2004GB2C0 is protocol compatible with previous generation 2Kbit devices such as the TSE2002. The page selection method
allows commands used with legacy devices such as TSE2002 to be applied to the lower or upper pages of the TSE2004GB2C0. In this
way, the TSE2004GB2C0 may be used in legacy applications without software changes. Minor exceptions to this compatibility, such as
elimination of the Permanent Write Protect feature are documented.
Individually locking a 128-byte block of the SPD may be accomplished using a software write protection mechanism in conjunction with a
high input voltage VHV on input SA0. By sending the device a specific SMBus sequence, each block may be protected from writes until
Write protection is electrically reversed using a separate SMBus sequence, which also requires VHV on input SA0. Write protection for all
four blocks is cleared simultaneously, and Write protection may be reasserted after being cleared.
The Thermal Sensor (TS) section of the TSE2004GB2C0 continuously monitors the temperature, and updates the temperature data a
minimum of eight times per second. Temperature data is latched internally by the device and may be read by software from the bus host
at any time.
Internal registers are used to configure both the TS performance and response to over-temperature conditions. The device contains
programmable high, low, and critical temperature limits. Finally, the device EVENT_n pin can be configured as active high or active low,
and can be configured to operate as an interrupt or as a comparator output.
Figure 5. Device Diagram
SDA
VSSSPD
SCL
SA0
SA1
SA2
SPD
EVENT_n
VDDSPD


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