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TSE2004GB2C0NCG データシート(PDF) 7 Page - Integrated Device Technology |
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TSE2004GB2C0NCG データシート(HTML) 7 Page - Integrated Device Technology |
7 / 38 page 7 ©2017 Integrated Device Technology, Inc. May 15, 2017 TSE2004GB2C0 Datasheet Device Interface The TSE2004GB2C0 functions as a slave device in the I2C Bus protocol with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a START condition generated by the bus master. The START condition is followed by a Device Select Code and R/W# bit (Table 2), and terminated by an acknowledge bit. The TSE2004GB2C0 does not initiate clock stretching, which is an optional I2C Bus feature. In accordance with the I2C Bus definition, the device uses three built-in 4-bit Device Type Identifier Codes (DTIC), and the state of SA0, SA1, and SA2 to generate an I2C Bus Slave Address. The SPD memory may be accessed using a DTIC of (1010), and to perform the SWPn, RSPn, or CSWP operations, a DTIC of (0110) is required. The TS registers are accessed using a DTIC of (0011). Serial Address Selection SA0, SA1, and SA2 inputs are directly combined with the DTIC and the EE page address bit to qualify SMBus addresses. Each of the SAx pins are tied to VDDSPD or VSSSPD, and the Logical Serial Address (LSA) is equal to the code on the Serial Address pins. Table 2. I2C Bus Addressing Modes[a] [a] 0 = VSSSPD, 1 = VDDSPD. Logical Serial Address (LSA) SA2 SA1 SA0 000 0 0 0 001 0 0 1 010 0 1 0 011 0 1 1 100 1 0 0 |
同様の部品番号 - TSE2004GB2C0NCG |
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同様の説明 - TSE2004GB2C0NCG |
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