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TSEV8308500GLZA2 データシート(PDF) 7 Page - ATMEL Corporation |
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TSEV8308500GLZA2 データシート(HTML) 7 Page - ATMEL Corporation |
7 / 50 page 7 TS8308500 2193A–BDC–04/03 Notes: 1. Differential output buffers are internally loaded by 75 Ω resistors. Buffer bias current = 11 mA 2. See “Definition of Terms” on page 46 3. Histogram testing based on sampling of a 10 MHz sinewave at 50 Msps 4. Output error amplitude < ±4 lsb around worst code 5. Maximum jitter value obtained for single-ended clock input on the die (chip on board): 200 fs 6. Digital output back termination options depicted in Application Notes 7. At 500 Msps, 50/50 clock duty cycle, TC2 = 2 ns (TC1). TDR - TOD = -100 ps (typ) does not depend on the sampling rate 8. Specified loading conditions for digital outputs: - 50 Ω or 75Ω controlled impedance traces properly 50/75Ω terminated, or unterminated 75Ω controlled impedance traces - Controlled impedance traces far end loaded by 1 standard ECLinPS register from Motorola. (i.e.: 10E452) (Typical input parasitic capacitance of 1.5 pF including package and ESD protections.) 9. Termination load parasitic capacitance derating values: - 50 Ω or 75Ω controlled impedance traces properly 50/75Ω terminated: 60 ps/pF or 75 ps per additionnal ECLinPS load Spurious free dynamic range SFDR – – – – – (2) F S = 500 Msps, FIN = 20 MHz – 4 50 56 – dBc FS = 500 Msps, FIN = 500 MHz – 4 50 53 – dBc F S = 500 Msps, FIN = 1000 MHz (-1 dBFS) – 4 38 40 – dBc F S = 50 Msps, FIN = 25 MHz – 1 50 55 – dBc Two-tone inter-modulation distortion IMD 4 – – – – (2) F IN1 = 199.5 MHz at FS = 500 Msps, FIN2 = 200.5 MHz at FS = 500 Msps –– -47 -52 – dBc Switching Performance and Characteristics – See Figure 2 and Figure 3 on page 9 Maximum clock frequency F S – 500 – 700 Msps (12) Minimum clock frequency FS 410 – 50 Msps (13) Minimum clock pulse width (high) TC1 4 1.71 2 50 ns Minimum clock pulse width (low) TC2 4 1.71 2 50 ns Aperture delay Ta 4 100 +250 400 ps (2) Aperture uncertainty Jitter 4 – 0.4 0.6 ps (rms) (2)(5) Data output delay TDO 4 1150 1360 1660 ps (2)(8) (9)(10) Output rise/fall time for data (20%-80%) TR/TF 4 250 350 550 ps (9) Output rise/fall time for data ready (20%-80%) TR/TF 4 250 350 550 ps (9) Data ready output delay TDR 4 1110 1320 1620 ps (2)(8) (9)(10) Data ready reset delay TRDR 4 – 720 1000 ps Data to data ready – Clock low pulse width (See “Timing Diagrams” on page 9) TOD-TDR 4 0 40 80 ps (7)(11) (12) Data to data ready output delay (50% duty cycle) at 1 Gsps (See “Timing Diagrams” on page 9) TD1 4 920 960 1000 ps (2)(13) Data pipeline delay TPD 4 4 clock cycles Table 3. Electrical Specifications (Continued) Parameter Symbol Test Level Value Unit Note Min Typ Max |
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同様の説明 - TSEV8308500GLZA2 |
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