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AD9261BCPZRL7-10 データシート(PDF) 8 Page - Analog Devices |
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AD9261BCPZRL7-10 データシート(HTML) 8 Page - Analog Devices |
8 / 29 page AD9261 Rev. 0 | Page 7 of 28 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Rating Electrical AVDD to AGND −0.3 V to +2.0 V DVDD to DGND −0.3 V to +2.0 V DRVDD to DGND −0.3 V to +3.9 V AGND to DGND −0.3 V to +0.3 V AVDD to DRVDD −3.9 V to +2.0 V CVDD to CGND −0.3 V to +2.0 V CGND to DGND −0.3 V to +0.3 V D0 to D15 to DGND −0.3 V to +2.0 V DCO to DGND −0.3 V to +2.0 V OR to DGND −0.3 V to +2.0 V PDWN to GND −0.3 V to +2.0 V PLLMULTx to DGND −0.3 V to +2.0 V SDIO to DGND −0.3 V to +3.9 V CSB to AGND −0.3 V to +3.9 V SCLK to AGND −0.3 V to +3.9 V VIN+, VIN− to AGND −0.3 V to +2.5 V CLK+, CLK− to CGND −0.3 V to +2.0 V Environmental Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C Lead Temperature (Soldering, 10 Sec) 300°C Junction Temperature 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the PCB increases the reliability of the solder joints, maximizing the thermal capability of the package. Table 7. Thermal Resistance Package Type θJA θJB θJC Unit 48-Lead LFCSP (CP-48-1) 27.7 11.8 1.1 °C/W Typical θJA and θJC are specified for a 4-layer board in still air. Airflow increases heat dissipation, effectively reducing θJA. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces the θJA. ESD CAUTION |
同様の部品番号 - AD9261BCPZRL7-10 |
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同様の説明 - AD9261BCPZRL7-10 |
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