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ACE24AC256 データシート(PDF) 5 Page - ACE Technology Co., LTD. |
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ACE24AC256 データシート(HTML) 5 Page - ACE Technology Co., LTD. |
5 / 16 page ACE24AC256 Two-wire Serial EEPROM VER 1.2 5 Figure 2: Timing diagram for output acknowledge Device Addressing The 2-wire serial bus protocol mandates an 8 bits device address word after a start bit condition to invoke a valid read or write command. The first four most significant bits of the device address must be 1010, which is common to all serial EEPROM devices. The next three bits are device address bits. These three device address bits (5 th, 6th and 7th) are to match with the external chip select/address pin states. If a match is made, the EEPROM device outputs an acknowledge signal after the 8 th read/write bit, otherwise the chip will go into standby mode. However, matching may not be needed for some or all device address bits (5 th, 6thand 7th) as noted below. The last or 8th bit is a read/write command bit. If the 8th bit is at V IH then the chip goes into read mode. If a “0” is detected, the device enters programming mode. Write Operations (A) Byte Write A write operation requires two 8-bit data word address following the device address word and acknowledge signal. Upon receipt of this address, the EEPROM will respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will again output a “0”. The addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters into an internally-timed write cycle state. All inputs are disabled during this write cycle and the EEPROM will not respond until the writing is completed (figure 3). |
同様の部品番号 - ACE24AC256 |
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同様の説明 - ACE24AC256 |
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