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GS4576C36GL-25I データシート(PDF) 11 Page - GSI Technology |
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GS4576C36GL-25I データシート(HTML) 11 Page - GSI Technology |
11 / 63 page GS4576C09/18/36L Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.04 11/2013 11/62 © 2011, GSI Technology On–Die Termination (ODT) Mode Register Bit 9 (M9) set to 1 during an MRS command enables ODT. With ODT on, the DQs and DM are terminated to VTT with a resistance, RTT. Command, address, QVLD, and clock signals are not terminated. The diagram below shows the equivalent circuit of a DQ receiver with ODT. When a tri-stated DQ begins to drive, the ODT function is briefly switched off. When a DQ stops driving at the end of a data transfer, ODT is switched back on. Two-state DM pin never deactivates ODT. On–Die Termination DC Parameters Description Symbol Min Max Units Notes Termination Voltage VTT 0.95 * VREF 1.05 * VREF V 1, 2 On–Die Termination RTT 125 185 3 Notes: 1. All voltages referenced to VSS (GND). 2. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF. 3. The RTT value is measured at 95°C TC. VTT SW RTT Receiver DQ VREF On–Die Termination–Equivalent Circuit |
同様の部品番号 - GS4576C36GL-25I |
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同様の説明 - GS4576C36GL-25I |
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