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GS8673ED18BK-550I データシート(PDF) 4 Page - GSI Technology

部品番号 GS8673ED18BK-550I
部品情報  72Mb SigmaQuad-IIIe??Burst of 4 ECCRAM?
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メーカー  GSI [GSI Technology]
ホームページ  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS8673ED18BK-550I データシート(HTML) 4 Page - GSI Technology

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GS8673ED18/36BK-675/625/550/500
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.06 5/2012
4/31
© 2011, GSI Technology
Pin Description
Symbol
Description
Type
SA
Address—Read or Write Address is registered on
↑CK.
Input
D[35:0]
Write Data—Registered on
↑KD and ↑KD during Write operations.
D[17:0]—x18 and x36.
D[35:18]—x36 only.
Input
Q[35:0]
Read Data—Driven by
↑CK and ↑CK, and synchronized with ↑CQ and ↑CQ during Read operations.
Q[17:0]—x18 and x36.
Q[35:18]—x36 only.
Output
QVLD[1:0]
Read Data Valid—Driven high one half cycle before valid Read Data.
Output
CK, CK
Primary Input Clocks—Dual single-ended. For Address and Control input latching, internal timing control,
and Read Data and Echo Clock output timing control.
Input
KD[1:0],
KD[1:0]
Write Data Input Clocks—Dual single-ended. For Write Data input latching.
KD0, KD0—latch Write Data (D[17:0] in x36, D[8:0] in x18).
KD1, KD1—latch Write Data (D[35:18] in x36, D[17:9] in x18).
Input
CQ[1:0],
CQ[1:0]
Echo Clocks—Free running source synchronous output clocks.
Output
R
Read Enable—Registered on
↑CK. R = 0 initiates a Read operation.
Input
W
Write Enable—Registered on
↑CK. W = 0 initiates a Write operation.
Input
ADZT1
Address and Write Data Input Termination Pull-Up Enable—Registered on
↑CK.
ADZT1 = 0: enables termination pull-up on Address (SA), Write Data (D) inputs.
ADZT1 = 1: disables termination pull-up on Address (SA), Write Data (D) inputs.
Input
DLL
DLL Enable—Weakly pulled High internally.
DLL = 0: disables internal DLL.
DLL = 1: enables internal DLL.
Input
RST
Reset—Holds the device inactive and resets the device to its initial power-on state when asserted High.
Weakly pulled Low internally.
Input
RLM[1:0]
Read Latency Select 1:0—Must be tied High or Low.
RLM[1:0] = 00: reserved.
RLM[1:0] = 01: selects 2.0 cycle Read Latency.
RLM[1:0] = 10: selects 3.0 cycle Read Latency.
RLM[1:0] = 11: reserved.
Input
ZQ
Output Driver Impedance Control Resistor Input—Must be connected to VSS through an external
resistor RQ to program output driver impedance.
Input
ZT
Input Termination Impedance Control Resistor Input—Must be connected to VSS through an external
resistor RT to program input termination impedance.
Input


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