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GS4576C09L-24I データシート(PDF) 1 Page - GSI Technology |
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GS4576C09L-24I データシート(HTML) 1 Page - GSI Technology |
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1 / 63 page  GS4576C09/18/36L 64M x 9, 32M x 18, 16M x 36 576Mb CIO Low Latency DRAM (LLDRAM II) 533 MHz–300 MHz 2.5 V VEXT 1.8 V VDD 1.5 V or 1.8 V VDDQ 144-Ball BGA Commercial Temp Industrial Temp Rev: 1.04 11/2013 1/62 © 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Features • Pin- and function-compatible with Micron RLDRAM® II • 533 MHz DDR operation (1.067Gb/s/pin data rate) • 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock frequency) • 16M x 36, 32M x 18, and 64M x 9 organizations available • 8 banks • Reduced cycle time (15 ns at 533 MHz) • Address Multiplexing (Nonmultiplexed address option available) • SRAM-type interface • Programmable Read Latency (RL), row cycle time, and burst sequence length • Balanced Read and Write Latencies in order to optimize data bus utilization • Data mask for Write commands • Differential input clocks (CK, CK) • Differential input data clocks (DKx, DKx) • On-chip DLL generates CK edge-aligned data and output data clock signals • Data valid signal (QVLD) • 32 ms refresh (16K refresh for each bank; 128K refresh command must be issued in total each 32 ms) • 144-ball BGA package • HSTL I/O (1.5 V or 1.8 V nominal) • 25 –60 matched impedance outputs • 2.5 V VEXT, 1.8 V VDD, 1.5 V or 1.8 V VDDQ I/O • On-die termination (ODT) RTT • Commerical and Industrial Temperature Commercial (+0° T C +95°C) Industrial (–40° T C +95°C) Introduction The GSI Technology 576Mb Low Latency DRAM (LLDRAM II) is a high speed memory device designed for high address rate data processing typically found in networking and telecommunications applications. The 8-bank architecture and low tRC allows access rates formerly only found in SRAMs. The Double Data Rate (DDR) I/O interface provides high bandwidth data transfers, clocking out two beats of data per clock cycle at the I/O balls. Source-synchronous clocking can be implemented on the host device with the provided free- running data output clock. Commands, addresses, and control signals are single data rate signals clocked in by the True differential input clock transition, while input data is clocked in on both crossings of the input data clock(s). Read and Write data transfers always in short bursts. The burst length is programmable to 2, 4 or 8 by setting the Mode Register. The device is supplied with 2.5 V VEXT and 1.8 V VDD for the core, and 1.5 V or 1.8 V for the HSTL output drivers. Internally generated row addresses facilitate bank-scheduled refresh. The device is delivered in an efficent BGA 144-ball package. |
同様の部品番号 - GS4576C09L-24I |
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同様の説明 - GS4576C09L-24I |
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