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TLV8544PWR データシート(PDF) 5 Page - Texas Instruments

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部品番号 TLV8544PWR
部品情報  500-nA, RRIO, Nanopower Operational Amplifiers for Cost-Optimized Systems
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
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TLV8544PWR データシート(HTML) 5 Page - Texas Instruments

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TLV8544, TLV8541, TLV8542
www.ti.com
SNOSD29B – DECEMBER 2016 – REVISED JUNE 2017
Product Folder Links: TLV8544 TLV8541 TLV8542
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails must
be current-limited to 10 mA or less.
(3)
If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(4)
Short-circuit to ground.
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)
(1) (2) (3)
MIN
MAX
UNIT
Supply voltage, Vs = (V+) – (V–)
–0.3
4
V
Input pins
Voltage
Common mode
(V–) – 0.3
(V+) + 0.3
V
Differential
(V–) – 0.3
(V+) + 0.3
V
Input pins
Current
–10
10
mA
Output short current(4)
Continuous
Continuous
Operating ambient temperature
–40
125
°C
Storage temperature, Tstg
–65
150
°C
Junction temperature
150
°C
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
(2)
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±750 V may actually have higher performance.
6.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±1000
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±250
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Supply voltage (V+ – V–)
1.7
3.6
V
Specified ambient temperature
–40
125
°C
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information
THERMAL METRIC(1)
TLV8544
TLV8542
UNIT
PW (TSSOP)
D (SOIC)
14 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
124.5
141.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
52.7
85.7
°C/W
RθJB
Junction-to-board thermal resistance
66.2
84.7
°C/W
ψJT
Junction-to-top characterization parameter
7.3
36.3
°C/W
ψJB
Junction-to-board characterization parameter
65.7
84.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W


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