Bit4:

0 -> Fixed priority

Functional Description

1 -> Rotating priority

The C8237 core is partitioned into modules as shown in the

block diagram and described below:

Bit5:

0 -> Late write

1 -> Extended write

Timing & Control

X -> if bit3 = 1

It generates internal timing and external control signals for the

C8237. The timing Control block derives internal timing from

the clock input. The C8237 operates in two major cycles, idle

cycle (Si) and Active cycle (S0, S1, S2, S3, and S4). Memory-

to-memory transfers require a read-from and a write-to-

memory to complete each transfer. It requires eight states for

a single transfer. The first four states (S11, S12, S13, S14)

are used for the read-from –memory half and the last four

states (S21, S22, S23, S24) for the write-to-memory half of

the transfer. Each state is composed of one full clock period.

Bit6:

0 -> DREQ sense active high

1 -> DREQ sense active low

Bit7:

0 -> DACK sense active low

1 -> DACK sense active high

Mode Register

Write Mode Register Command:

A3

A2

A1

A0

IORN

IOWN

1

0

1

1

1

0

Fixed Priority & Rotating Priority Logic

Each channel has a 6-bit Mode register. It is programmed by

the microprocessor.

The Fixed Priority fixes the channels in priority order based

upon the descending value of their number. The lowest prior-

ity channel is 3 and the highest priority channel is 0.

With Rotating Priority, the last channel to get service be-

comes the lowest priority channel with the others rotating

accordingly.

D7

D6

D5

D4

D3

D2

D1

D0

Bit1 & Bit0: 00 -> Channel 0

01 -> Channel 1

C8237 Registers

10 -> Channel 2

The C8237 contains 344 bits of internal memory in the form

of registers. CSN must be low when the microprocessor is at-

tempting to write or read the internal registers of the C8237.

11 -> Channel 3

Bit3 & Bit2: 00 -> Verify transfer (pseudo transfer)

Command Register

01 -> Write transfer (from I/O to the memory)

Write Command Register Command:

10 -> Read transfer (from the memory to I/O)

A3

A2

A1

A0

IORN

IOWN

1

0

0

0

1

0

11 -> Illegal

XX -> if bits 6 and 7 = 11

This 8-bit register controls the operation of the C8237. It is

programmed by the microprocessor and is cleared by Reset

or a Master Clear instruction.

Bit4: 0 -> Auto initialization disable

1 -> Auto initialization enable

Bit5: 0 -> Address increment select

D7

D6

D5

D4

D3

D2

D1

D0

1 -> Address decrement select

Bit0:

0 -> Memory-to-memory disable

Bit7 & Bit6: 00 -> Demand mode

1 -> Memory-to-memory enable

01 -> Single mode

Bit1:

0 -> Channel 0 address hold disable

10 -> Block mode

1 -> Channel 0 address hold enable

11 -> Cascade mode

X -> if bit0 = 0

Demand Transfer Mode: The device will continue making

transfers until a TC or external EOPN is encountered or until

DREQ goes inactive.

Bit2:

0 -> Controller enable

1 -> Controller disable

Bit3:

0 -> Normal timing

Single Transfer Mode: The device makes one transfer only.

DREQ must be held active until DACK becomes active in or-

der to be recognized.

1 -> Compressed timing

X -> if bit 0 = 1

Block Transfer Mode: The device is active by DREQ or

software request to continue making transfers during the ser-

vice until a TC or an external EOPN is encountered. DREQ

need only be held active until DACK becomes active.

Cascade Transfer Mode: This mode is used to cascade

more than one C8237 together for simple system expansion.

The ready input is ignored in this cascade transfer mode.

Cast, Inc.

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