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GS8673ED36BK-550I データシート(PDF) 9 Page - GSI Technology

部品番号 GS8673ED36BK-550I
部品情報  On-Chip ECC with virtually zero SER
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メーカー  GSI [GSI Technology]
ホームページ  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS8673ED36BK-550I データシート(HTML) 9 Page - GSI Technology

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GS8673ED18/36BK-675/625/550/500
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.06 5/2012
9/31
© 2011, GSI Technology
Functional Description
Separate I/O ECCRAMs, from a system architecture point of view, are attractive in applications that execute continuous
back-to-back alternating Reads and Writes. Therefore, the SigmaQuad-IIIe ECCRAM interface and truth table are optimized for
continuously alternating Reads and Writes. Separate I/O ECCRAMs are unpopular in applications where block transfers of Reads
or Writes are needed because half of the data pins will go unused during the block transfer, potentially cutting Separate I/O
ECCRAM data bandwidth in half. Applications of this sort are better served by Common I/O ECCRAMs such as the
SigmaDDR-IIIe series.
Truth Table
Previous
Operation
SA
R
W
Current
Operation
D
Q
(tn–1)
↑CK
(tn)
↑CK
(tn)
↑CK
(tn)
(tn)
↑KD
(tn+1)
↑KD
(tn+1½)
↑KD
(tn+2)
↑KD
(tn+2½)
↑CK
(tm)
↑CK
(tm+180º)
↑CK
(tm+1)
↑CK
(tm+1+180º)
NOP
X
1
1
NOP
X
X
Hi-Z/0
Hi-Z/0
Write
X
1
X
NOP
D3
D4
Hi-Z/0
Hi-Z/0
Read
X
X
1
NOP
X
X
Q3
Q4
NOP
V
1
0
Write
D1
D2
D3
D4
Hi-Z/0
Hi-Z/0
Read
V
X
0
Write
D1
D2
D3
D4
Q3
Q4
NOP
V
0
X
Read
X
X
Q1
Q2
Q3
Q4
Write
V
0
X
Read
D3
D4
Q1
Q2
Q3
Q4
Notes:
1. 1 = input High; 0 = input Low; V = input valid; X = input don’t care.
2. tm= tn + RL, where RL = Read Latency of the device.
3. D1, D2, D3, and D4 indicate the first, second, third, and fourth pieces of Write Data transferred during Write operations.
4. Q1, Q2, Q3, and Q4 indicate the first, second, third, and fourth pieces of Read Data transferred during Read operations.
5. When D input termination is disabled (MZT[1:0] = 00), Q drivers are disabled (i.e. Q pins are tri-stated) for one cycle in response to NOP and
Write commands, RL cycles after the command is sampled, except when preceded by a Read command.
6. When D input termination is enabled (MZT[1:0] = 01 or 10), Q drivers are enabled Low (i.e. Q pins are driven Low) for one cycle in response
to NOP and Write commands, RL cycles after the command is sampled, except when preceded by a Read command. This is done so the
Memory Controller can enable On-Die Termination on its data inputs without having to cope with the termination pulling tri-stated data inputs
to VDDQ/2 (i.e., to the switch point of the data input receivers).


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