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GS8673ED36BK-550IS データシート(PDF) 5 Page - GSI Technology |
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GS8673ED36BK-550IS データシート(HTML) 5 Page - GSI Technology |
5 / 25 page GS8673ED18/36BK-725S/625S/550S Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.04 6/2015 5/25 © 2012, GSI Technology MVQ I/O Voltage Select — Indicates what voltage is supplied to the VDDQ pins. Must be tied High or Low. MVQ = 0: Configure for 1.2V or 1.35V nominal VDDQ. MVQ = 1: Configure for 1.5V nominal VDDQ. Input VDD Core Power Supply — 1.35V nominal core supply voltage. — VDDQ I/O Power Supply — 1.2V or 1.35V or 1.5V nominal I/O supply voltage. Configurable via MVQ pin. — VREF Input Reference Voltage — Input buffer reference voltage. — VSS Ground — TCK JTAG Clock Input TMS JTAG Mode Select — Weakly pulled High internally. Input TDI JTAG Data Input — Weakly pulled High internally. Input TDO JTAG Data Output Output MCH Must Connect High — May be tied to VDDQ directly or via a 1k resistor. Input MCL Must Connect Low — May be tied to VSS directly or via a 1k resistor. Input NC No Connect — There is no internal chip connection to these pins. They may be left unconnected, or tied High or Low. — NUI Not Used Input — There is an internal chip connection to these input pins, but they are unused by the device. They are pulled Low internally. They may be left unconnected or tied/driven Low. They should not be tied/driven High. Input NUO Not Used Output — There is an internal chip connection to these output pins, but they are unused by the device. The drivers are tri-stated internally. They should be left unconnected. Output Pin Description (Continued) Symbol Description Type |
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同様の説明 - GS8673ED36BK-550IS |
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