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GS8673EQ36BGK-625IS データシート(PDF) 8 Page - GSI Technology |
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GS8673EQ36BGK-625IS データシート(HTML) 8 Page - GSI Technology |
8 / 25 page GS8673EQ18/36BK-725S/625S/550S Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.03 6/2014 8/25 © 2012, GSI Technology Driver Impedance Control Programmable Driver Impedance is implemented on the following output signals: • CQ, CQ, Q, QVLD. Driver impedance is programmed by connecting an external resistor RQ between the ZQ pin and VSS. Driver impedance is set to the programmed value within 160K cycles after input clocks are operating within specification and RST is de-asserted Low. It is updated periodically thereafter to compensate for temperature and voltage fluctuations in the system. Output Signal Pull-Down Impedance (ROUTL) Pull-Up Impedance (ROUTH) CQ, CQ, Q, QVLD RQ*0.2 ± 15% RQ*0.2 ± 15% Notes: 1. ROUTL and ROUTH apply when 175Ω ≤ RQ ≤ 225Ω.. 2. The mismatch between ROUTL and ROUTH is less than 10%, guaranteed by design. ODT Impedance Control Programmable ODT Impedance is implemented on the following input signals: • CK, CK, KD, KD, SA, R, W, D. ODT impedance is programmed by connecting an external resistor RT between the ZT pin and VSS. ODT impedance is set to the programmed value within 160K cycles after input clocks are operating within specification and RST is de-asserted Low. It is updated periodically thereafter to compensate for temperature and voltage fluctuations in the system Input Signal PZT[1:0] MZT[1:0] Pull-Down Impedance (RINL) Pull-Up Impedance (RINH) CK, CK, KD, KD X0 XX disabled disabled X1 01 RT ± 15% RT ± 15% 10 RT*2 ± 20% RT*2 ± 20% SA, R, W 0X XX disabled disabled 1X 01 RT ± 15% RT ± 15% 10 RT*2 ± 20% RT*2 ± 20% D XX 01 RT ± 15% RT ± 15% 10 RT*2 ± 20% RT*2 ± 20% Notes: 1. When MZT[1:0] = 00, ODT is disabled on all inputs. MZT[1:0] = 11 is reserved for future use. 2. RINL and RINH apply when 105Ω ≤ RT ≤ 135Ω. 3. The mismatch between RINL and RINH is less than 10%, guaranteed by design. 4. All ODT is disabled during JTAG EXTEST and SAMPLE-Z instructions. Note: When ODT impedance is enabled on a particular input, that input should always be driven High or Low; it should never be tri-stated (i.e., in a High- Z state). If the input is tri-stated, the ODT will pull the signal to VDDQ / 2 (i.e., to the switch point of the diff-amp receiver), which could cause the receiver to enter a meta-stable state and consume more power than it normally would. This could result in the device’s operating currents being higher. |
同様の部品番号 - GS8673EQ36BGK-625IS |
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同様の説明 - GS8673EQ36BGK-625IS |
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