データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

GS81332QT19CE-350M データシート(PDF) 11 Page - GSI Technology

部品番号 GS81332QT19CE-350M
部品情報  Rad-Hard SRAM 288Mb/144Mb/72Mb Burst of 2 SigmaQuad-IITM
Download  30 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  GSI [GSI Technology]
ホームページ  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS81332QT19CE-350M データシート(HTML) 11 Page - GSI Technology

Back Button GS81332QT19CE-350M Datasheet HTML 7Page - GSI Technology GS81332QT19CE-350M Datasheet HTML 8Page - GSI Technology GS81332QT19CE-350M Datasheet HTML 9Page - GSI Technology GS81332QT19CE-350M Datasheet HTML 10Page - GSI Technology GS81332QT19CE-350M Datasheet HTML 11Page - GSI Technology GS81332QT19CE-350M Datasheet HTML 12Page - GSI Technology GS81332QT19CE-350M Datasheet HTML 13Page - GSI Technology GS81332QT19CE-350M Datasheet HTML 14Page - GSI Technology GS81332QT19CE-350M Datasheet HTML 15Page - GSI Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 11 / 30 page
background image
GS82612QT19/37CE-350M/250M
GS81332QT19/37CE-350M/250M
GS8692QT19/37CE-350M/250M
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 7/2017
11/30
© 2017, GSI Technology
Preliminary
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad-II+ SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 175
 and 350. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is
implemented with discrete binary weighted impedance steps.
Input Termination Impedance Control
These SigmaQuad-II+ SRAMs are supplied with programmable input termination on Data (D), Byte Write (BW), and Clock (K,K)
input receivers. The input termination is always enabled, and the impedance is programmed via the same RQ resistor (connected
between the ZQ pin and VSS) used to program output driver impedance, in conjuction with the ODT pin (6R). When the ODT pin
is tied Low, input termination is "strong" (i.e., low impedance), and is nominally equal to RQ*0.3 Thevenin-equivalent when RQ is
between 175Ω and 350Ω. When the ODT pin is tied High (or left floating—the pin has a small pull-up resistor), input termination
is "weak" (i.e., high impedance), and is nominally equal to RQ*0.6 Thevenin-equivalent when RQ is between 175Ω and 250Ω.
Periodic readjustment of the termination impedance occurs to compensate for drifts in supply voltage and temperature, in the same
manner as for driver impedance (see above).
Note:
D, BW, K, K inputs should always be driven High or Low; they should never be tri-stated (i.e., in a High-Z state). If the inputs are
tri-stated, the input termination will pull the signal to VDDQ/2 (i.e., to the switch point of the diff-amp receiver), which could cause
the receiver to enter a meta-stable state, resulting in the receiver consuming more power than it normally would. This could result
in the device’s operating currents being higher.
Power-Up Initialization
After power-up, stable input clocks must be applied to the device for 20
s prior to issuing read and write commands. See the tKInit
timing parameter in the AC Electrical Characteristics section.
Note:
The tKInit requirement is independent of the tLock requirement, which specifies how many cycles of stable input clocks (2048)
must be applied after the Doff pin has been driven High in order to ensure that the DLL locks properly (and the DLL must lock
properly before issuing read and write commands). However, tKInit is greater than tKLock, even at the slowest permitted cycle time
of 8.4 ns (2048*8.4 ns = 17.2
s). Consequently, the 20 s associated with tKInit is sufficient to cover the tKLock requirement at
power-up if the Doff pin is driven High prior to the start of the 20
s period.
Also, tKInit only needs to be met once, immediately after power-up, whereas tKLock must be met any time the DLL is disabled/reset
(whether by toggling Doff Low or by stopping K clocks for > 30 ns).


同様の部品番号 - GS81332QT19CE-350M

メーカー部品番号データシート部品情報
logo
GSI Technology
GS81332QT19CE-250M GSI-GS81332QT19CE-250M Datasheet
1Mb / 30P
   Rad-Hard SRAM 288Mb/144Mb/72Mb Burst of 2 SigmaQuad-II 1.8
More results

同様の説明 - GS81332QT19CE-350M

メーカー部品番号データシート部品情報
logo
GSI Technology
GS82612QT19CE-350M GSI-GS82612QT19CE-350M Datasheet
1Mb / 30P
   Rad-Hard SRAM 288Mb/144Mb/72Mb Burst of 2 SigmaQuad-IITM
GS81332QT37CE-350M GSI-GS81332QT37CE-350M Datasheet
1Mb / 30P
   Rad-Hard SRAM 288Mb/144Mb/72Mb Burst of 2 SigmaQuad-IITM
GS81332QT19CE-250M GSI-GS81332QT19CE-250M Datasheet
1Mb / 30P
   Rad-Hard SRAM 288Mb/144Mb/72Mb Burst of 2 SigmaQuad-II 1.8
GS82582Q19GE-400 GSI-GS82582Q19GE-400 Datasheet
436Kb / 25P
   288Mb SigmaQuad-IITM Burst of 2 SRAM
GS82582Q37GE-300 GSI-GS82582Q37GE-300 Datasheet
436Kb / 25P
   288Mb SigmaQuad-IITM Burst of 2 SRAM
GS82582QT19GE-400I GSI-GS82582QT19GE-400I Datasheet
325Kb / 26P
   288Mb SigmaQuad-IITM Burst of 2 SRAM
GS82582Q19GE-400I GSI-GS82582Q19GE-400I Datasheet
436Kb / 25P
   288Mb SigmaQuad-IITM Burst of 2 SRAM
GS82582Q37GE-400 GSI-GS82582Q37GE-400 Datasheet
436Kb / 25P
   288Mb SigmaQuad-IITM Burst of 2 SRAM
GS82582QT20GE-450I GSI-GS82582QT20GE-450I Datasheet
325Kb / 26P
   288Mb SigmaQuad-IITM Burst of 2 SRAM
GS82582Q19GE-333 GSI-GS82582Q19GE-333 Datasheet
436Kb / 25P
   288Mb SigmaQuad-IITM Burst of 2 SRAM
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30


データシート ダウンロード

Go To PDF Page


リンク URL




プライバシーポリシー
ALLDATASHEET.JP
ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com