Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.00a 5/2017

5/26

© 2017, GSI Technology

GS81302DT20/38AGD-633/550/500/450

Preliminary

Background

Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are

needed. Therefore, the SigmaQuad-II+ SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O

SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from

Separate I/O SRAMs can cut the RAM’s bandwidth in half.

SigmaQuad-II+ Burst of 4 SRAM DDR Read

The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A Low on

the Read Enable pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command. Clocking

in a High on the Read Enable pin, R, begins a read port deselect cycle.

SigmaQuad-II+ Burst of 4 SRAM DDR Write

The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R High causes chip disable. A Low on

the Write Enable pin, W, and a High on the Read Enable pin, R, begins a write cycle. W is always ignored if the previous command

was a write command. Data is clocked in by the next rising edge of K, the rising edge of K after that, the next rising edge of K, and

finally by the next rising edge of K.

Special Functions

Byte Write Control

Byte Write Enable pins are sampled at the same time that Data In is sampled. A High on the Byte Write Enable pin associated with

a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be

stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven High or Low

during the data in sample times in a write sequence.

Each write enable command and write address loaded into the RAM provides the base address for a 4-beat data transfer. The x18

version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any

write sequence.

Example x18 RAM Write Sequence using Byte Write Enables

Data In Sample Time

BW0

BW1

D0–D8

D9–D17

Beat 1

0

1

Data In

Don’t Care

Beat 2

1

0

Don’t Care

Data In

Beat 3

0

0

Data In

Data In

Beat 4

1

0

Don’t Care

Data In

Resulting Write Operation

Byte 1

D0–D8

Byte 2

D9–D17

Byte 1

D0–D8

Byte 2

D9–D17

Byte 1

D0–D8

Byte 2

D9–D17

Byte 1

D0–D8

Byte 2

D9–D17

Written

Unchanged

Unchanged

Written

Written

Written

Unchanged

Written

Beat 1

Beat 2

Beat 3

Beat 4