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GS8672D36BE-200 データシート(PDF) 5 Page - GSI Technology |
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GS8672D36BE-200 データシート(HTML) 5 Page - GSI Technology |
5 / 29 page GS8672D18/36BE-400/333/300/250/200 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.02a 8/2017 5/29 © 2011, GSI Technology Background Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are needed. Therefore, the SigmaQuad-II ECCRAM interface and truth table are optimized for alternating reads and writes. Separate I/O SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from Separate I/O SRAMs can cut the RAM’s bandwidth in half. SigmaQuad-II ECCRAM DDR Read The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A Low on the Read Enable pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command. Data can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C are tied high), after the following rising edge of K with a rising edge of C (or by K if C and C are tied High), after the next rising edge of K with a rising edge of C, and after the following rising edge of K with a rising edge of C. Clocking in a High on the Read Enable pin, R, begins a read port deselect cycle. SigmaQuad-II ECCRAM DDR Write The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A Low on the Write Enable pin, W, and a high on the Read Enable pin, R, begins a write cycle. W is always ignored if the previous command was a write command. Data is clocked in by the next rising edge of K, the rising edge of K after that, the next rising edge of K, and finally by the next rising edge of K. |
同様の部品番号 - GS8672D36BE-200 |
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同様の説明 - GS8672D36BE-200 |
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