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GS8672Q18BGE-300 データシート(PDF) 6 Page - GSI Technology

部品番号 GS8672Q18BGE-300
部品情報  72Mb SigmaQuad-II Burst of 2 ECCRAM
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メーカー  GSI [GSI Technology]
ホームページ  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS8672Q18BGE-300 データシート(HTML) 6 Page - GSI Technology

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GS8672Q18/36BE-400/333/300/250/200
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02a 8/2017
6/28
© 2011, GSI Technology
Power-Up Sequence for SigmaQuad-II ECCRAMs
SigmaQuad-II ECCRAMs must be powered-up in a specific sequence in order to avoid undefined operations.
1. After power supplies power-up and clocks (K, K) are stablized, 163,840 cycles are required to set Output Driver
Impedance.
2. Thereafter, an additional 65,536 clock cycles are required to lock the DLL after it has been enabled.
3. Begin Read and Write operations.
For more information, read AN1021 SigmaQuad and SigmaDDR Power-Up.
On-Chip Error Correction
SigmaQuad-II ECCRAMs implement a single-bit error detection and correction algorithm (specifically, a Hamming Code) on each
DDR data word (comprising two 9-bit data bytes) transmitted on each 9-bit data bus (i.e., transmitted on D/Q[8:0], D/Q[17:9], D/
Q[26:18], or D/Q[35:27]). To accomplish this, 5 ECC parity bits (invisible to the user) are utilized per every 18 data bits (visible to
the user).
The ECC algorithm neither corrects nor detects multi-bit errors. However, GSI ECCRAMs are architected in such a way that a
single SER event very rarely causes a multi-bit error across any given "transmitted data unit", where a "transmitted data unit"
represents the data transmitted as the result of a single read or write operation to a particular address. The extreme rarity of multi-
bit errors results in the SER mentioned previously (i.e., <0.002 FITs/Mb measured at sea level).
Not only does the on-chip ECC significantly improve SER performance, but it also frees up the entire memory array for data
storage. Very often SRAM applications allocate 1/9th of the memory array (i.e., one "error bit" per eight "data bits", in any 9-bit
"data byte") for error detection (either simple parity error detection, or system-level ECC error detection and correction). Such
error-bit allocation is unnecessary with ECCRAMs —the entire memory array can be utilized for data storage, effectively
providing 12.5% greater storage capacity compared to SRAMs of the same density not equipped with on-chip ECC.
Output Register Control
SigmaQuad-II ECCRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the
Output Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing
of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of
the K and K clocks. If the C and C clock inputs are tied High, the RAM reverts to K and K control of the outputs, allowing the
RAM to function as a conventional pipelined read ECCRAM.


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