GS8672D19/37BE-450/400/375/333/300

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.02c 8/2017

5/28

© 2011, GSI Technology

Background

Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are

needed. Therefore, the SigmaQuad-II+ ECCRAM interface and truth table are optimized for alternating reads and writes. Separate

I/O SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers

from Separate I/O SRAMs can cut the RAM’s bandwidth in half.

SigmaQuad-II+ B4 ECCRAM DDR Read

The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on

the Read Enable-bar pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command.

Clocking in a high on the Read Enable-bar pin, R, begins a read port deselect cycle.

SigmaQuad-II+ B4 ECCRAM DDR Write

The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on

the Write Enable-bar pin, W, and a high on the Read Enable-bar pin, R, begins a write cycle. W is always ignored if the previous

command was a write command. Data is clocked in by the next rising edge of K, the rising edge of K after that, the next rising edge

of K, and finally by the next rising edge of K. and by the rising edge of the K that follows.