AD9208BBPZ-3000 datasheet(5/137 Pages) AD

部品番号	AD9208BBPZ-3000

部品情報	14-Bit, 3 GSPS, JESD204B, Dual Analog-to-Digital Converter

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AD9208

Data Sheet

Rev. 0 | Page 4 of 136

GENERAL DESCRIPTION

The AD9208 is a dual, 14-bit, 3 GSPS analog-to-digital converter

(ADC). The device has an on-chip buffer and a sample-and-

hold circuit designed for low power, small size, and ease of use.

This product is designed to support communications applications

capable of direct sampling wide bandwidth analog signals of up

to 5 GHz. The −3 dB bandwidth of the ADC input is 9 GHz.

The AD9208 is optimized for wide input bandwidth, high sampling

rate, excellent linearity, and low power in a small package.

The dual ADC cores feature a multistage, differential pipelined

architecture with integrated output error correction logic. Each

ADC features wide bandwidth inputs supporting a variety of

user-selectable input ranges. An integrated voltage reference

eases design considerations. The analog input and clock signals

are differential inputs. The ADC data outputs are internally

connected to four digital downconverters (DDCs) through a

crossbar mux. Each DDC consists of up to five cascaded signal

processing stages: a 48-bit frequency translator (numerically

controlled oscillator (NCO)), and up to four half-band decimation

filters. The NCO has the option to select preset bands over the

general-purpose input/output (GPIO) pins, which enables the

selection of up to three bands. Operation of the AD9208 between

the DDC modes is selectable via SPI-programmable profiles.

In addition to the DDC blocks, the AD9208 has several functions

that simplify the automatic gain control (AGC) function in a

communications receiver. The programmable threshold detector

allows monitoring of the incoming signal power using the fast

detect control bits in Register 0x0245 of the ADC. If the input

signal level exceeds the programmable threshold, the fast detect

indicator goes high. Because this threshold indicator has low

latency, the user can quickly turn down the system gain to avoid

an overrange condition at the ADC input. In addition to the fast

detect outputs, the AD9208 also offers signal monitoring

capability. The signal monitoring block provides additional

information about the signal being digitized by the ADC.

The user can configure the Subclasss 1 JESD204B-based high

speed serialized output in a variety of one-lane, two-lane, four-

lane, and eight-lane configurations, depending on the DDC

configuration and the acceptable lane rate of the receiving logic

device. Multidevice synchronization is supported through the

SYSREF± and SYNCINB± input pins.

The AD9208 has flexible power-down options that allow

significant power savings when desired. All of these features can

be programmed using a 3-wire serial port interface (SPI).

The AD9208 is available in a Pb-free, 196-ball BGA, specified

over the −40°C to +85°C ambient temperature range. This

product is protected by a U.S. patent.

Note that throughout this data sheet, multifunction pins, such

as FD_A/GPIO_A0, are referred to either by the entire pin

name or by a single function of the pin, for example, FD_A,

when only that function is relevant.

PRODUCT HIGHLIGHTS

1.

Wide, input −3 dB bandwidth of 9 GHz supports direct radio

frequency (RF) sampling of signals up to about 5 GHz.

2.

Four integrated, wideband decimation filter and NCO

blocks supporting multiband receivers.

3.

Fast NCO switching enabled through the GPIO pins.

4.

A SPI controls various product features and functions to

meet specific system requirements.

5.

Programmable fast overrange detection and signal

monitoring.

6.

On-chip temperature diode for system thermal management.

7.

12 mm × 12 mm, 196-ball BGA.

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