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AD9208BBPZRL-3000 データシート(PDF) 10 Page - Analog Devices |
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AD9208BBPZRL-3000 データシート(HTML) 10 Page - Analog Devices |
10 / 137 page Data Sheet AD9208 Rev. 0 | Page 9 of 136 SWITCHING SPECIFICATIONS AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.9 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.9 V, SPIVDD = 1.9 V, specified maximum sampling rate, 1.7 V p-p full-scale differential input, AIN = −2.0 dBFS, default SPI settings, −10°C ≤ TJ ≤ +120°C,1 unless otherwise noted. Typical specifications represent performance at TJ = 70°C (TA = 25°C). Table 4. Parameter Min Typ Max Unit CLOCK Clock Rate (at CLK+/CLK− Pins) 3 6 GHz Sample Rate2 2500 3000 3100 MSPS Clock Pulse Width High 161.29 166.67 192.31 ps Clock Pulse Width Low 161.29 166.67 192.31 ps OUTPUT PARAMETERS Unit Interval (UI)3 62.5 66.67 592.6 ps Rise Time (tR) (20% to 80% into 100 Ω Load) 26 ps Fall Time (tF) (20% to 80% into 100 Ω Load) 26 ps Phase-Locked Loop (PLL) Lock Time 5 ms Data Rate per Channel (Nonreturn to Zero)4 1.6875 15 16 Gbps LATENCY5 Pipeline Latency6 75 Clock cycles Fast Detect Latency 26 Clock cycles WAKE-UP TIME Standby 400 μs Power-Down 15 ms NCO CHANNEL SELECTION TO OUTPUT 8 Clock cycles APERTURE Aperture Delay (tA) 250 ps Aperture Uncertainty (Jitter, tJ) 55 fs rms Out of Range Recovery Time 1 Clock cycles 1 The junction temperature (TJ) range of −10°C to +120°C translates to an ambient temperature (TA) range of −40°C to +85°C. 2 The maximum sample rate is the clock rate after the divider. 3 Baud rate = 1/UI. A subset of this range can be supported. 4 Default L = 8. This number can be changed based on the sample rate and decimation ratio. 5 No DDCs used. L = 8, M = 2, and F = 1. 6 Refer to the Latency section for more details. |
同様の部品番号 - AD9208BBPZRL-3000 |
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同様の説明 - AD9208BBPZRL-3000 |
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